公开(公告)号：US20240155842A1

公开(公告)日：2024-05-09

申请号：US18510736

申请日：2023-11-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyo Joon RYU ,  Seo-Goo KANG ,  Hee Suk KIM ,  Jong Seon AHN ,  Kohji KANAMORI ,  Jee Hoon HAN

IPC: H10B43/27 ,  H01L23/522 ,  H10B41/27

CPC classification number: H10B43/27 ,  H01L23/5226 ,  H10B41/27

Abstract: A semiconductor memory device includes a lower stacked structure with lower metal lines on a substrate, an upper stacked structure with an upper metal line on the lower stacked structure, a vertical structure penetrating the upper and lower stacked structures and including a channel layer, a first cutting line through the upper and lower stacked structures, an upper supporter in a recess on the first cutting line, a second cutting line through the upper and lower stacked structures and spaced apart from the first cutting line, a sub-cutting line through the upper stacked structure while at least partially overlapping the vertical structure in the vertical direction, the sub-cutting line being between the first and second cutting lines, top surfaces of the upper supporter and sub-cutting line being coplanar, and a first interlayer insulating layer surrounding a sidewall of each of the upper supporter and the sub-cutting line.

公开(公告)号：US20220278125A1

公开(公告)日：2022-09-01

申请号：US17747174

申请日：2022-05-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jong Seon AHN ,  Ji Sung CHEON ,  Young Jin KWON ,  Seok Cheon BAEK ,  Woong Seop LEE

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L29/423 ,  H01L27/11573 ,  H01L21/28 ,  H01L27/11565

Abstract: A three-dimensional semiconductor device includes an upper substrate, a gate-stacked structure on the upper substrate, the gate-stacked structure including gate electrodes stacked within a memory cell array region, while being spaced apart from each other in a direction perpendicular to a surface of the upper substrate, and extending into an extension region adjacent to the memory cell array region to be arranged within the extension region to have a staircase shape, and at least one through region passing through the gate-stacked structure within the memory cell array region or the extension region, the at least one through region including a lower region and an upper region wider than the lower region.

公开(公告)号：US20190214404A1

公开(公告)日：2019-07-11

申请号：US16257357

申请日：2019-01-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong Seon AHN ,  Ji Sung CHEON ,  Young Jin KWON ,  Seok Cheon BAEK ,  Woong Seop LEE

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11573 ,  H01L21/28 ,  H01L29/423

CPC classification number: H01L27/11582 ,  H01L21/28282 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/4234

Abstract: A three-dimensional semiconductor device includes an upper substrate, a gate-stacked structure on the upper substrate, the gate-stacked structure including gate electrodes stacked within a memory cell array region, while being spaced apart from each other in a direction perpendicular to a surface of the upper substrate, and extending into an extension region adjacent to the memory cell array region to be arranged within the extension region to have a staircase shape, and at least one through region passing through the gate-stacked structure within the memory cell array region or the extension region, the at least one through region including a lower region and an upper region wider than the lower region.