公开(公告)号：US20220278125A1

公开(公告)日：2022-09-01

申请号：US17747174

申请日：2022-05-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jong Seon AHN ,  Ji Sung CHEON ,  Young Jin KWON ,  Seok Cheon BAEK ,  Woong Seop LEE

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L29/423 ,  H01L27/11573 ,  H01L21/28 ,  H01L27/11565

Abstract: A three-dimensional semiconductor device includes an upper substrate, a gate-stacked structure on the upper substrate, the gate-stacked structure including gate electrodes stacked within a memory cell array region, while being spaced apart from each other in a direction perpendicular to a surface of the upper substrate, and extending into an extension region adjacent to the memory cell array region to be arranged within the extension region to have a staircase shape, and at least one through region passing through the gate-stacked structure within the memory cell array region or the extension region, the at least one through region including a lower region and an upper region wider than the lower region.

公开(公告)号：US20230292515A1

公开(公告)日：2023-09-14

申请号：US18321080

申请日：2023-05-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-Hwan SON ,  Kohji KANAMORI ,  Shin-Hwan KANG ,  Young Jin KWON

IPC: H10B43/27 ,  H01L23/535 ,  H10B43/40

CPC classification number: H10B43/27 ,  H01L23/535 ,  H10B43/40

Abstract: A vertical memory device includes gate electrodes on a substrate, a channel extending through the gate electrodes, and a contact plug extending through the gate electrodes. The gate electrodes are stacked in a first direction substantially vertical to an upper surface of the substrate and arranged to have a staircase shape including steps of which extension lengths in a second direction substantially parallel to the upper surface gradually increase from a lowermost level toward an uppermost level. A pad at an end portion of each of the gate electrodes in the second direction has a thickness greater than those of other portions thereof. The channel extends in the first direction. The contact plug extends in the first direction. The channel contacts the pad of a first gate electrode among the gate electrodes to be electrically connected thereto, and is electrically insulated from second gate electrodes among the gate electrodes.

公开(公告)号：US20190214404A1

公开(公告)日：2019-07-11

申请号：US16257357

申请日：2019-01-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong Seon AHN ,  Ji Sung CHEON ,  Young Jin KWON ,  Seok Cheon BAEK ,  Woong Seop LEE

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11573 ,  H01L21/28 ,  H01L29/423

CPC classification number: H01L27/11582 ,  H01L21/28282 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/4234

Abstract: A three-dimensional semiconductor device includes an upper substrate, a gate-stacked structure on the upper substrate, the gate-stacked structure including gate electrodes stacked within a memory cell array region, while being spaced apart from each other in a direction perpendicular to a surface of the upper substrate, and extending into an extension region adjacent to the memory cell array region to be arranged within the extension region to have a staircase shape, and at least one through region passing through the gate-stacked structure within the memory cell array region or the extension region, the at least one through region including a lower region and an upper region wider than the lower region.