公开(公告)号：US20170082921A1

公开(公告)日：2017-03-23

申请号：US15218284

申请日：2016-07-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jong-su KIM ,  Shuichi TAMAMUSHI ,  In-kyun SHIN ,  Sung-il LEE ,  Jin CHOI

IPC: G03F1/70 ,  G03F1/72

CPC classification number: G03F1/70 ,  G03F1/78 ,  G03F7/2059 ,  G03F7/70616 ,  G03F7/70875

Abstract: A method of manufacturing a reticle, the method including preparing a substrate, determining position data of a pattern to be formed on the substrate, and setting a primary exposure condition to form the pattern; performing a primary exposure simulation regarding the substrate based on the position data of the pattern and the primary exposure condition; calculating a primary deformation rate of the substrate, which is generated in the primary exposure simulation; correcting the position data of the pattern based on the primary deformation rate of the substrate to provide a corrected position data of the pattern; and exposing the substrate under the primary exposure condition based on the corrected position data of the pattern.

公开(公告)号：US20160027739A1

公开(公告)日：2016-01-28

申请号：US14736455

申请日：2015-06-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki-hyun Park ,  Byoung-ho KWON ,  Dong-chan KIM ,  Choong-seob SHIN ,  Jong-su KIM ,  Bo-un YOON

IPC: H01L23/544 ,  H01L21/66 ,  H01L21/768 ,  H01L21/4757 ,  H01L21/033

CPC classification number: H01L23/544 ,  H01L21/47573 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/7684 ,  H01L22/12 ,  H01L2223/54426 ,  H01L2223/5446 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of manufacturing a semiconductor device includes forming a first alignment mark trench in a first material layer on a substrate. A first alignment mark via may then be formed by etching a second material layer that is underneath the first material layer, where the first alignment mark via is positioned to communicate with the first alignment mark trench. Then, a trench-via-merged-type first alignment mark may be formed by filling the first alignment mark trench and the first alignment mark via with a light reflection material layer.

Abstract translation: 一种制造半导体器件的方法包括在衬底上的第一材料层中形成第一对准标记沟槽。 然后可以通过蚀刻在第一材料层下面的第二材料层来形成第一对准标记通孔，其中第一对准标记通孔被定位成与第一对准标记沟槽连通。 然后，可以通过用光反射材料层填充第一对准标记沟槽和第一对准标记通孔来形成沟槽合并型第一对准标记。