公开(公告)号：US09812220B2

公开(公告)日：2017-11-07

申请号：US15207557

申请日：2016-07-12

申请人： Samsung Electronics Co., Ltd.

发明人： Tae-Hyung Kim ,  Huichong Shin ,  Seokil Kim ,  Young Yun ,  Jonghyoung Lim ,  Youkeun Han

IPC分类号： G11C7/10 ,  G11C29/34 ,  G06F3/06 ,  G06F12/1009 ,  G11C11/4076 ,  G11C11/4093 ,  G11C5/04

CPC分类号： G11C29/34 ,  G06F3/0613 ,  G06F3/0647 ,  G06F3/0656 ,  G06F3/0688 ,  G06F12/0868 ,  G06F12/1009 ,  G06F2212/1016 ,  G06F2212/1024 ,  G11C5/04 ,  G11C7/1045 ,  G11C7/109 ,  G11C11/4076 ,  G11C11/4093 ,  G11C29/06 ,  G11C29/26 ,  G11C2029/0407

摘要： A method of operating a memory module including a plurality of semiconductor memory devices organized into a multi-rank memory on a DIMM and a memory buffer included on the DIMM, operatively coupled to the multi-rank memory, can be provided by mapping an access to the DIMM from a memory controller to semiconductor memory devices included in more than one rank within the multi-rank memory based on a mode register set signal and selectively linking rank control signals during a parallel bit test operation to the more than one rank within the multi-rank memory plurality of semiconductor memory devices.

公开(公告)号：US09922724B2

公开(公告)日：2018-03-20

申请号：US15713936

申请日：2017-09-25

申请人： Samsung Electronics Co., Ltd.

发明人： Tae-Hyung Kim ,  Huichong Shin ,  Seokil Kim ,  Young Yun ,  Jonghyoung Lim ,  Youkeun Han

IPC分类号： G11C7/10 ,  G11C29/34 ,  G06F3/06 ,  G06F12/1009 ,  G11C11/4093 ,  G11C11/4076 ,  G11C5/04

CPC分类号： G11C29/34 ,  G06F3/0613 ,  G06F3/0647 ,  G06F3/0656 ,  G06F3/0688 ,  G06F12/0868 ,  G06F12/1009 ,  G06F2212/1016 ,  G06F2212/1024 ,  G11C5/04 ,  G11C7/1045 ,  G11C7/109 ,  G11C11/4076 ,  G11C11/4093 ,  G11C29/06 ,  G11C29/26 ,  G11C2029/0407

摘要： A method of operating a memory module including a plurality of semiconductor memory devices organized into a multi-rank memory on a DIMM and a memory buffer included on the DIMM, operatively coupled to the multi-rank memory, can be provided by mapping an access to the DIMM from a memory controller to semiconductor memory devices included in more than one rank within the multi-rank memory based on a mode register set signal and selectively linking rank control signals during a parallel bit test operation to the more than one rank within the multi-rank memory plurality of semiconductor memory devices.

公开(公告)号：US20170092379A1

公开(公告)日：2017-03-30

申请号：US15207557

申请日：2016-07-12

申请人： Samsung Electronics Co., Ltd.

发明人： Tae-Hyung Kim ,  Huichong Shin ,  Seokil Kim ,  Young Yun ,  Jonghyoung Lim ,  Youkeun Han

IPC分类号： G11C29/34 ,  G06F12/1009 ,  G06F3/06 ,  G11C11/4093 ,  G11C11/4076

CPC分类号： G11C29/34 ,  G06F3/0613 ,  G06F3/0647 ,  G06F3/0656 ,  G06F3/0688 ,  G06F12/0868 ,  G06F12/1009 ,  G06F2212/1016 ,  G06F2212/1024 ,  G11C5/04 ,  G11C7/1045 ,  G11C7/109 ,  G11C11/4076 ,  G11C11/4093 ,  G11C29/06 ,  G11C29/26 ,  G11C2029/0407

摘要： A method of operating a memory module including a plurality of semiconductor memory devices organized into a multi-rank memory on a DIMM and a memory buffer included on the DIMM, operatively coupled to the multi-rank memory, can be provided by mapping an access to the DIMM from a memory controller to semiconductor memory devices included in more than one rank within the multi-rank memory based on a mode register set signal and selectively linking rank control signals during a parallel bit test operation to the more than one rank within the multi-rank memory plurality of semiconductor memory devices.