公开(公告)号：US09171755B2

公开(公告)日：2015-10-27

申请号：US14453310

申请日：2014-08-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Euibok Lee ,  Jongmin Baek ,  Dohyoung Kim ,  Tsukasa Matsuda ,  Youngwoo Cho ,  Jongseo Hong

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/764 ,  H01L21/762

CPC classification number: H01L21/7682 ,  H01L21/02296 ,  H01L21/3105 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/762 ,  H01L21/764 ,  H01L21/76802 ,  H01L21/76849 ,  H01L21/76882 ,  H01L21/76883 ,  H01L21/76885

Abstract: A method of manufacturing a semiconductor device may include: forming an interlayer insulating layer having openings on a substrate; forming a metal layer in the openings and on the interlayer insulating layer, the metal layer including a sidewall portion on a sidewall of each of the openings and a bottom portion on a bottom surface of each of the openings, wherein the bottom portion is thicker than the sidewall portion; reflowing the metal layer to form metal patterns in the openings, the metal patterns having top surfaces at a level lower than a topmost surface of the interlayer insulating layer; and/or forming capping patterns covering the metal patterns in the openings.

Abstract translation: 制造半导体器件的方法可以包括：在衬底上形成具有开口的层间绝缘层; 在开口和层间绝缘层上形成金属层，金属层包括在每个开口的侧壁上的侧壁部分和在每个开口的底表面上的底部，其中底部部分比 侧壁部分; 回流金属层以在开口中形成金属图案，金属图案具有位于层间绝缘层的最上表面以下的顶表面; 和/或形成覆盖开口中的金属图案的覆盖图案。