公开(公告)号：US11227870B2

公开(公告)日：2022-01-18

申请号：US16739392

申请日：2020-01-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joo-Heon Kang ,  Tae Hun Kim ,  Jae Ryong Sim ,  Kwang Young Jung ,  Gi Yong Chung ,  Jee Hoon Han ,  Doo Hee Hwang

IPC: H01L27/11578 ,  H01L27/11582 ,  H01L27/1157

Abstract: A semiconductor memory device includes a third insulating pattern and a first insulating pattern on a substrate, the third insulating pattern and the first insulating pattern being spaced apart from each other in a first direction that is perpendicular to the substrate such that a bottom surface of the third insulating pattern and a top surface of the first insulating pattern face each other, a gate electrode between the bottom surface of the third insulating pattern and the top surface of the first insulating pattern, and including a first side extending between the bottom surface of the third insulating pattern and the top surface of the first insulating pattern, and a second insulating pattern that protrudes from the first side of the gate electrode by a second width in a second direction, the second direction being different from the first direction.

公开(公告)号：US10008389B2

公开(公告)日：2018-06-26

申请号：US15408926

申请日：2017-01-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joo-Heon Kang ,  Jae-Joo Shim

IPC: H01L21/311 ,  H01L27/11582

CPC classification number: H01L21/31144 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582

Abstract: A method of manufacturing a vertical memory device includes forming a preliminary first mold structure on a substrate, which includes main and edge regions, and the first preliminary mold structure including alternating insulation and sacrificial layers, forming a first mask on the preliminary first mold structure to expose the preliminary first mold structure between a boundary of the substrate and a first target position, partially etching the insulation and sacrificial layers using the first mask to form a preliminary second mold structure, forming a second mask on the preliminary second mold structure to expose the preliminary second mold structure between the boundary of the substrate and a second target position different from the first target position, and partially etching the insulation layers and the sacrificial layers using the second mask.

公开(公告)号：US11974433B2

公开(公告)日：2024-04-30

申请号：US17575947

申请日：2022-01-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joo-Heon Kang ,  Tae Hun Kim ,  Jae Ryong Sim ,  Kwang Young Jung ,  Gi Yong Chung ,  Jee Hoon Han ,  Doo Hee Hwang

IPC: H10B43/27 ,  H10B43/35

CPC classification number: H10B43/27 ,  H10B43/35

Abstract: A semiconductor memory device includes a third insulating pattern and a first insulating pattern on a substrate, the third insulating pattern and the first insulating pattern being spaced apart from each other in a first direction that is perpendicular to the substrate such that a bottom surface of the third insulating pattern and a top surface of the first insulating pattern face each other, a gate electrode between the bottom surface of the third insulating pattern and the top surface of the first insulating pattern, and including a first side extending between the bottom surface of the third insulating pattern and the top surface of the first insulating pattern, and a second insulating pattern that protrudes from the first side of the gate electrode by a second width in a second direction, the second direction being different from the first direction.

公开(公告)号：US10784281B2

公开(公告)日：2020-09-22

申请号：US16425349

申请日：2019-05-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joo-Heon Kang ,  Bongtae Park ,  Jae-Joo Shim

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L21/02 ,  H01L21/311 ,  H01L27/1157

Abstract: A 3D semiconductor memory device includes an electrode structure on a substrate, the electrode structure including gate electrodes stacked in a first direction perpendicular to a top surface of the substrate, a vertical semiconductor pattern penetrating the electrode structure and connected to the substrate, and a data storage pattern between the electrode structure and the vertical semiconductor pattern. The data storage pattern includes first, second and third insulating patterns sequentially stacked. Each of the first to third insulating patterns includes a horizontal portion extending in a second direction parallel to the top surface of the substrate. The horizontal portions of the first, second and third insulating patterns are sequentially stacked in the first direction. At least one of the horizontal portions of the first and third insulating patterns protrudes beyond a sidewall of the horizontal portion of the second insulating pattern in the second direction.