公开(公告)号：US20240357799A1

公开(公告)日：2024-10-24

申请号：US18508833

申请日：2023-11-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Choong Hyun LEE ,  Joon Cheol KIM ,  Kang-Uk KIM ,  Jin A KIM ,  Byoung Wook JANG ,  Young-Seung CHO

IPC: H10B12/00 ,  G11C5/06

CPC classification number: H10B12/482 ,  G11C5/063 ,  H10B12/315 ,  H10B12/485 ,  H10B12/488 ,  H10B12/50

Abstract: There is provided a semiconductor memory device capable of improving performance and reliability of an element. The semiconductor memory device includes a substrate including a cell region and a peripheral region, a cell region isolation layer in the substrate, isolating the cell region from the peripheral region, an isolation active region surrounded by the cell region isolation layer, a bit line structure on the cell region, including a cell conductive line and a cell gate electrode in the substrate of the cell region, crossing the cell conductive line.