公开(公告)号：US20240224501A1

公开(公告)日：2024-07-04

申请号：US18483693

申请日：2023-10-10

申请人： Samsung Electronics Co., Ltd.

发明人： Jooncheol KIM ,  Kang-Uk KIM

IPC分类号： H10B12/00

CPC分类号： H10B12/315 ,  H10B12/482

摘要： A semiconductor memory device including a substrate including a cell area and a peripheral area around the cell area, a cell area isolation film in the substrate and defining the cell area, a bit-line structure in the cell area, a peripheral gate structure in the peripheral area of the substrate, the peripheral gate structure including a peripheral gate conductive film, a peripheral spacer on a sidewall of the peripheral gate structure, an etch stop film on the peripheral spacer and spaced apart from the peripheral gate structure, a first peripheral insulating film around the peripheral gate structure on the substrate, and a peripheral interlayer insulating film covering the peripheral gate structure, the first peripheral insulating film, and the peripheral spacer, the peripheral interlayer insulating film including a material different from a material of the first peripheral insulating film, may be provided.

公开(公告)号：US20240357799A1

公开(公告)日：2024-10-24

申请号：US18508833

申请日：2023-11-14

申请人： Samsung Electronics Co., Ltd.

发明人： Choong Hyun LEE ,  Joon Cheol KIM ,  Kang-Uk KIM ,  Jin A KIM ,  Byoung Wook JANG ,  Young-Seung CHO

IPC分类号： H10B12/00 ,  G11C5/06

CPC分类号： H10B12/482 ,  G11C5/063 ,  H10B12/315 ,  H10B12/485 ,  H10B12/488 ,  H10B12/50

摘要： There is provided a semiconductor memory device capable of improving performance and reliability of an element. The semiconductor memory device includes a substrate including a cell region and a peripheral region, a cell region isolation layer in the substrate, isolating the cell region from the peripheral region, an isolation active region surrounded by the cell region isolation layer, a bit line structure on the cell region, including a cell conductive line and a cell gate electrode in the substrate of the cell region, crossing the cell conductive line.

公开(公告)号：US20240107751A1

公开(公告)日：2024-03-28

申请号：US18352528

申请日：2023-07-14

申请人： Samsung Electronics Co., Ltd.

发明人： Jin A KIM ,  Kang-Uk KIM ,  Sang Hoon MIN ,  Choong Hyun LEE

IPC分类号： H10B12/00

CPC分类号： H10B12/485 ,  H10B12/312 ,  H10B12/482 ,  H10B12/488

摘要： A semiconductor memory device is provided. The semiconductor memory device comprises a substrate including a cell region having an active region defined by a cell element isolation layer, a peripheral region near the cell region, and a boundary region between the cell region and the peripheral region. The device includes a word line structure in the substrate and extending in a first direction, a bit line structure on the substrate extending from the cell region to the boundary region in a second direction that crosses the first direction, including first and second cell conductive layers sequentially stacked on the substrate, and a bit line contact between the substrate and the bit line structure and connecting the substrate with the bit line structure. The second cell conductive layer in the boundary region is thicker than the second cell conductive layer in the cell region.

公开(公告)号：US20150303201A1

公开(公告)日：2015-10-22

申请号：US14591165

申请日：2015-01-07

申请人： Samsung Electronics Co., Ltd.

发明人： Dongjin LEE ,  Sungho JANG ,  Jiyoung KIM ,  Kang-Uk KIM ,  Chan Min LEE ,  Juyeon JANG

IPC分类号： H01L27/108 ,  H01L21/768 ,  H01L21/285 ,  H01L21/311

CPC分类号： H01L27/10885 ,  H01L21/32134 ,  H01L21/32135 ,  H01L21/32139 ,  H01L27/10888 ,  H01L27/10894 ,  H01L27/10897

摘要： Semiconductor devices, and methods for forming the same, include forming a first wiring film and an etching buffer film in a cell array region and a peripheral circuit region of a substrate, and forming a contact hole by selectively etching the etching buffer film and the first wiring film so as to expose an active region of the cell array region and at least a part of a field isolation region adjacent thereto. A bit line contact is formed in the contact hole to be in contact with the active region, and a second wiring film is formed over the substrate. By patterning the second wiring film, the bit line contact, the etching buffer film, and the first wiring film, a bit line is formed in the cell array region and a peripheral gate is formed in the peripheral circuit region.

摘要翻译： 半导体器件及其形成方法包括在基板的单元阵列区域和外围电路区域中形成第一布线膜和蚀刻缓冲膜，并且通过选择性蚀刻蚀刻缓冲膜和第一布线膜形成接触孔 布线膜以暴露电池阵列区域的有源区域和与其相邻的场隔离区域的至少一部分。 在接触孔中形成与有源区接触的位线接触，在基板上形成第二布线膜。 通过图案化第二布线膜，位线接触，蚀刻缓冲膜和第一布线膜，在单元阵列区域中形成位线，并且在外围电路区域中形成周边栅极。