公开(公告)号：US20240347524A1

公开(公告)日：2024-10-17

申请号：US18403022

申请日：2024-01-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joonho Jun ,  Kyomin Sohn ,  Duksung Kim ,  Byoungkon Jo ,  Jangseok Choi

IPC: H01L25/18 ,  H01L23/00 ,  H01L25/00 ,  H10B80/00

CPC classification number: H01L25/18 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/16 ,  H01L25/50 ,  H10B80/00 ,  H01L24/80 ,  H01L24/94 ,  H01L2224/0557 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/08145 ,  H01L2224/16145 ,  H01L2224/80357 ,  H01L2224/94 ,  H01L2924/1436

Abstract: A semiconductor package according to an example embodiment of the present disclosure includes: a package substrate; and first to third memory dies disposed on the package substrate and sequentially stacked in a first direction, perpendicular to an upper surface of the package substrate, and the first memory die and the second memory die are attached to each other without a bump, and the second memory die and the third memory die are attached to each other by a plurality of bumps.

公开(公告)号：US11222873B2

公开(公告)日：2022-01-11

申请号：US16936882

申请日：2020-07-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joonho Jun ,  Un-Byoung Kang ,  Sunkyoung Seo ,  Jongho Lee ,  Young Kun Jee

IPC: H01L25/065 ,  H01L23/00

Abstract: A semiconductor package may include first and second substrates, which are vertically stacked, a semiconductor device layer on a bottom surface of the second substrate to face a top surface of the first substrate, upper chip pads and an upper dummy pad on the top surface of the first substrate, penetration electrodes, which each penetrate the first substrate and are connected to separate, respective upper chip pads, lower chip pads on a bottom surface of the semiconductor device layer and electrically connected to separate, respective upper chip pads, and a lower dummy pad on the bottom surface of the semiconductor device layer and electrically isolated from the upper dummy pad. A distance between the upper and lower dummy pads in a horizontal direction that is parallel to the first substrate may be smaller than a diameter of the lower dummy pad.

公开(公告)号：US11688707B2

公开(公告)日：2023-06-27

申请号：US17307672

申请日：2021-05-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joonho Jun ,  Sangsick Park ,  Unbyoung Kang

IPC: H01L25/065 ,  H01L23/00

CPC classification number: H01L24/13 ,  H01L24/05 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/05017 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05551 ,  H01L2224/05644 ,  H01L2224/13021 ,  H01L2224/16146 ,  H01L2224/16147 ,  H01L2224/16148 ,  H01L2225/06513

Abstract: Provided is a semiconductor package including: a first substrate having a first electrode pad and a first protective layer in which a cavity is formed; a first bump pad arranged in the cavity and connected to the first electrode pad; a second substrate facing the first substrate and having a second bump pad; and a bump structure in contact with the first bump pad and the second bump pad, wherein the first electrode pad has a trapezoidal shape, and the first bump pad has a flat upper surface and an inclined side surface extending along a side surface of the first electrode pad.

公开(公告)号：US20250062303A1

公开(公告)日：2025-02-20

申请号：US18663211

申请日：2024-05-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joonho Jun ,  Duksung Kim ,  Gyesik Oh ,  Minwoo Lee ,  Wangyong Im ,  Byoungkon Jo

IPC: H01L25/18 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48

Abstract: A semiconductor package may include a package substrate; a plurality of upper dies on an upper side of the package substrate and arranged so as not to overlap each other vertically; a plurality of electrical connection structures between the plurality of upper dies and the package substrate and electrically connected to the package substrate; a lower die on the package substrate and arranged so as not to vertically overlap with the plurality of electrical connection structures; and a plurality of overlapped electrical connection structures arranged between the plurality of upper dies and an upper surface of the lower die and electrically connected to the upper surface of the lower die. Each of the plurality of upper dies may include a plurality of memory dies that overlap each other vertically.

公开(公告)号：US20240371831A1

公开(公告)日：2024-11-07

申请号：US18488152

申请日：2023-10-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joonho Jun ,  Duk Sung Kim ,  Gyesik Oh ,  Minwoo Lee ,  Wangyong Im ,  Byoungkon Jo

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/538 ,  H10B80/00

Abstract: A semiconductor apparatus includes a semiconductor layer having a first surface and a second surface that is opposite to the first surface; a first wire structure on the first surface of the semiconductor layer; a second wire structure on the second surface of the semiconductor layer; a through via that extends through the semiconductor layer and is electrically connected to the first wire structure and the second wire structure; a first semiconductor element layer that is adjacent to the first surface of the semiconductor layer and in the semiconductor layer; and a second semiconductor element layer that is adjacent to the second surface of the semiconductor layer and in the semiconductor layer.

公开(公告)号：US11935873B2

公开(公告)日：2024-03-19

申请号：US18176058

申请日：2023-02-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joonho Jun ,  Un-Byoung Kang ,  Sunkyoung Seo ,  Jongho Lee ,  Young Kun Jee

IPC: H01L25/065 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L24/06 ,  H01L24/14 ,  H01L2224/0401 ,  H01L2224/06181 ,  H01L2224/06515 ,  H01L2225/06513

Abstract: A semiconductor package may include first and second substrates, which are vertically stacked, a semiconductor device layer on a bottom surface of the second substrate to face a top surface of the first substrate, upper chip pads and an upper dummy pad on the top surface of the first substrate, penetration electrodes, which each penetrate the first substrate and are connected to separate, respective upper chip pads, lower chip pads on a bottom surface of the semiconductor device layer and electrically connected to separate, respective upper chip pads, and a lower dummy pad on the bottom surface of the semiconductor device layer and electrically isolated from the upper dummy pad. A distance between the upper and lower dummy pads in a horizontal direction that is parallel to the first substrate may be smaller than a diameter of the lower dummy pad.

公开(公告)号：US11621250B2

公开(公告)日：2023-04-04

申请号：US17571796

申请日：2022-01-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joonho Jun ,  Un-Byoung Kang ,  Sunkyoung Seo ,  Jongho Lee ,  Young Kun Jee

IPC: H01L25/065 ,  H01L23/00

Abstract: A semiconductor package may include first and second substrates, which are vertically stacked, a semiconductor device layer on a bottom surface of the second substrate to face a top surface of the first substrate, upper chip pads and an upper dummy pad on the top surface of the first substrate, penetration electrodes, which each penetrate the first substrate and are connected to separate, respective upper chip pads, lower chip pads on a bottom surface of the semiconductor device layer and electrically connected to separate, respective upper chip pads, and a lower dummy pad on the bottom surface of the semiconductor device layer and electrically isolated from the upper dummy pad. A distance between the upper and lower dummy pads in a horizontal direction that is parallel to the first substrate may be smaller than a diameter of the lower dummy pad.

公开(公告)号：US20220020713A1

公开(公告)日：2022-01-20

申请号：US17307672

申请日：2021-05-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joonho Jun ,  Sangsick Park ,  Unbyoung Kang

IPC: H01L23/00 ,  H01L25/065

Abstract: Provided is a semiconductor package including: a first substrate having a first electrode pad and a first protective layer in which a cavity is formed; a first bump pad arranged in the cavity and connected to the first electrode pad; a second substrate facing the first substrate and having a second bump pad; and a bump structure in contact with the first bump pad and the second bump pad, wherein the first electrode pad has a trapezoidal shape, and the first bump pad has a flat upper surface and an inclined side surface extending along a side surface of the first electrode pad.