公开(公告)号：US20250008749A1

公开(公告)日：2025-01-02

申请号：US18615116

申请日：2024-03-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyundong LEE ,  Youngmin KIM ,  Joonseok OH ,  Sangyun LEE ,  Changbo LEE

IPC: H10B80/00 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L25/065 ,  H01L25/10

Abstract: A semiconductor package includes a substrate structure having a bridge chip therein; a semiconductor memory device on a first upper surface of the substrate structure and electrically connected to the bridge chip; and a semiconductor logic device on the first upper surface of the substrate structure and spaced apart from the semiconductor memory device, and the semiconductor logic device electrically connected to the bridge chip. The semiconductor memory device may include a redistribution wiring layer on the substrate structure and having a plurality of redistribution wirings; a plurality of buffer dies on a second upper surface of the redistribution wiring layer and electrically connected to the bridge chip through the plurality of redistribution wirings; and a plurality of semiconductor chips sequentially stacked on each of the plurality of buffer dies and electrically connected to the plurality of buffer dies.

公开(公告)号：US20230142301A1

公开(公告)日：2023-05-11

申请号：US18053806

申请日：2022-11-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Changbo LEE ,  Joonseok OH ,  Youngmin KIM ,  Jihye SHIN ,  Hyundong LEE

IPC: H01L23/498 ,  H01L25/10 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L23/49894 ,  H01L24/16 ,  H01L25/105 ,  H01L23/49816 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/182 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/18301

Abstract: A semiconductor package includes a first redistribution structure including a plurality of first redistribution layers and a plurality of first redistribution vias. A semiconductor chip is on the first redistribution structure. The semiconductor chip includes a chip pad. A connection pad is between the first redistribution structure and the semiconductor chip, and is connected to the first redistribution structure. A connection bump is connected to the connection pad and the chip pad. A molding layer extends around the first redistribution structure and the semiconductor chip, and a through electrode extends through the molding layer. A wetting layer is between the first redistribution structure and the molding layer.

公开(公告)号：US20220399260A1

公开(公告)日：2022-12-15

申请号：US17672092

申请日：2022-02-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoonyoung JEON ,  Joonseok OH ,  Youngmin KIM ,  Dongheon KANG ,  Changbo LEE

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/10 ,  H01L25/065

Abstract: A semiconductor package may include at least one first rewiring structure, the at least one first rewiring structure including a plurality of first insulating layers vertically stacked and a plurality of first rewiring patterns included in the plurality of first insulating layers, at least one semiconductor chip on the at least one first rewiring structure, and at least one molding layer covering the at least one semiconductor chip, wherein each of the plurality of first rewiring patterns includes, a first conductive pattern, the first conductive pattern including a curved upper surface, and a first seed pattern covering a side surface and a lower surface of the first conductive pattern, and each of the first seed patterns of the plurality of first rewiring patterns having a same shape.