公开(公告)号：US20210384136A1

公开(公告)日：2021-12-09

申请号：US17406517

申请日：2021-08-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Changbo LEE ,  Joonseok Oh ,  Byunglyul Park

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56

Abstract: This invention provides a fan-out semiconductor package ,the fan-out semiconductor package includes a frame including one or more insulating layers and having a penetration portion, a semiconductor chip disposed in the penetration portion of the frame and having a connection pad, a connection structure disposed on a lower side of the frame and the semiconductor chip and including a redistribution layer, a first encapsulant covering a back surface of the semiconductor chip and a first region of a top surface of an uppermost insulating layer among the one or more insulating layers of the frame and extending between a sidewall of the penetration portion and a side surface of the semiconductor chip, and a second encapsulant covering a second region of the top surface of the uppermost insulating layer among the one or more insulating layers of the frame and being in contact with a side surface of the first encapsulant on the frame.

公开(公告)号：US20210242158A1

公开(公告)日：2021-08-05

申请号：US17070540

申请日：2020-10-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changbo LEE ,  KWANHOO SON ,  JOON SEOK OH

IPC: H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H01L23/31 ,  H01L21/56 ,  H01L21/683

Abstract: Disclosed are semiconductor devices and methods of fabricating the same. The method comprises providing a carrier substrate that includes a conductive layer, placing a semiconductor die on the carrier substrate, forming an insulating layer to cover the semiconductor die on the carrier substrate, forming a via hole to penetrate the insulating layer at a side of the semiconductor die and to expose the conductive layer of the carrier substrate, performing a plating process in which the conductive layer of the carrier substrate is used as a seed to form a via filling the via hole, forming a first redistribution layer on a first surface of the semiconductor die and the insulating layer, removing the carrier substrate, and forming a second redistribution layer on a second surface of the semiconductor die and the insulating layer, the first surface and the second surface being located opposite each other.

公开(公告)号：US20250096181A1

公开(公告)日：2025-03-20

申请号：US18969410

申请日：2024-12-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changbo LEE ,  KWANHOO SON ,  JOON SEOK OH

IPC: H01L23/00 ,  H01L21/56 ,  H01L21/683 ,  H01L21/768 ,  H01L23/31 ,  H01L23/522 ,  H01L23/528

Abstract: Disclosed are semiconductor devices and methods of fabricating the same. The method comprises providing a carrier substrate that includes a conductive layer, placing a semiconductor die on the carrier substrate, forming an insulating layer to cover the semiconductor die on the carrier substrate, forming a via hole to penetrate the insulating layer at a side of the semiconductor die and to expose the conductive layer of the carrier substrate, performing a plating process in which the conductive layer of the carrier substrate is used as a seed to form a via filling the via hole, forming a first redistribution layer on a first surface of the semiconductor die and the insulating layer, removing the carrier substrate, and forming a second redistribution layer on a second surface of the semiconductor die and the insulating layer, the first surface and the second surface being located opposite each other.

公开(公告)号：US20250008749A1

公开(公告)日：2025-01-02

申请号：US18615116

申请日：2024-03-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyundong LEE ,  Youngmin KIM ,  Joonseok OH ,  Sangyun LEE ,  Changbo LEE

IPC: H10B80/00 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L25/065 ,  H01L25/10

Abstract: A semiconductor package includes a substrate structure having a bridge chip therein; a semiconductor memory device on a first upper surface of the substrate structure and electrically connected to the bridge chip; and a semiconductor logic device on the first upper surface of the substrate structure and spaced apart from the semiconductor memory device, and the semiconductor logic device electrically connected to the bridge chip. The semiconductor memory device may include a redistribution wiring layer on the substrate structure and having a plurality of redistribution wirings; a plurality of buffer dies on a second upper surface of the redistribution wiring layer and electrically connected to the bridge chip through the plurality of redistribution wirings; and a plurality of semiconductor chips sequentially stacked on each of the plurality of buffer dies and electrically connected to the plurality of buffer dies.

公开(公告)号：US20230387059A1

公开(公告)日：2023-11-30

申请号：US18143983

申请日：2023-05-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changbo LEE ,  KWANHOO SON ,  JOON SEOK OH

IPC: H01L23/00 ,  H01L23/522 ,  H01L21/768 ,  H01L23/31 ,  H01L21/56 ,  H01L21/683 ,  H01L23/528

CPC classification number: H01L24/20 ,  H01L24/13 ,  H01L24/19 ,  H01L24/11 ,  H01L23/5226 ,  H01L21/76871 ,  H01L23/315 ,  H01L21/566 ,  H01L21/6835 ,  H01L23/5283 ,  H01L2224/214 ,  H01L2221/68359

Abstract: Disclosed are semiconductor devices and methods of fabricating the same. The method comprises providing a carrier substrate that includes a conductive layer, placing a semiconductor die on the carrier substrate, forming an insulating layer to cover the semiconductor die on the carrier substrate, forming a via hole to penetrate the insulating layer at a side of the semiconductor die and to expose the conductive layer of the carrier substrate, performing a plating process in which the conductive layer of the carrier substrate is used as a seed to form a via filling the via hole, forming a first redistribution layer on a first surface of the semiconductor die and the insulating layer, removing the carrier substrate, and forming a second redistribution layer on a second surface of the semiconductor die and the insulating layer, the first surface and the second surface being located opposite each other.

公开(公告)号：US20230142301A1

公开(公告)日：2023-05-11

申请号：US18053806

申请日：2022-11-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Changbo LEE ,  Joonseok OH ,  Youngmin KIM ,  Jihye SHIN ,  Hyundong LEE

IPC: H01L23/498 ,  H01L25/10 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L23/49894 ,  H01L24/16 ,  H01L25/105 ,  H01L23/49816 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/182 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/18301

Abstract: A semiconductor package includes a first redistribution structure including a plurality of first redistribution layers and a plurality of first redistribution vias. A semiconductor chip is on the first redistribution structure. The semiconductor chip includes a chip pad. A connection pad is between the first redistribution structure and the semiconductor chip, and is connected to the first redistribution structure. A connection bump is connected to the connection pad and the chip pad. A molding layer extends around the first redistribution structure and the semiconductor chip, and a through electrode extends through the molding layer. A wetting layer is between the first redistribution structure and the molding layer.

公开(公告)号：US20220399260A1

公开(公告)日：2022-12-15

申请号：US17672092

申请日：2022-02-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoonyoung JEON ,  Joonseok OH ,  Youngmin KIM ,  Dongheon KANG ,  Changbo LEE

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/10 ,  H01L25/065

Abstract: A semiconductor package may include at least one first rewiring structure, the at least one first rewiring structure including a plurality of first insulating layers vertically stacked and a plurality of first rewiring patterns included in the plurality of first insulating layers, at least one semiconductor chip on the at least one first rewiring structure, and at least one molding layer covering the at least one semiconductor chip, wherein each of the plurality of first rewiring patterns includes, a first conductive pattern, the first conductive pattern including a curved upper surface, and a first seed pattern covering a side surface and a lower surface of the first conductive pattern, and each of the first seed patterns of the plurality of first rewiring patterns having a same shape.