公开(公告)号：US20230387056A1

公开(公告)日：2023-11-30

申请号：US18057305

申请日：2022-11-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yunsun Jang ,  Jungtae Sung ,  Moorym Choi

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L23/535 ,  H01L27/11582 ,  H01L27/11573 ,  H01L25/00

CPC classification number: H01L24/08 ,  H01L25/0657 ,  H01L25/18 ,  H01L23/535 ,  H01L27/11582 ,  H01L27/11573 ,  H01L24/80 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/80006 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: Disclosed are three-dimensional semiconductor memory devices and electronic systems. The three-dimensional semiconductor memory device includes a first substrate that includes a cell array region and a contact region, a peripheral circuit structure on the first substrate, a cell array structure on the peripheral circuit structure wherein the cell array structure includes interlayer dielectric layers and gate electrodes that are alternately stacked, a dielectric layer on the stack structure, and a second substrate on the stack structure, a mold structure that penetrates the stack structure and includes a dielectric material, and a first through structure and a second through structure that penetrate the mold structure and are spaced apart from each other.

公开(公告)号：US20230140000A1

公开(公告)日：2023-05-04

申请号：US17834977

申请日：2022-06-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Moorym Choi ,  Jungtae Sung ,  Yunsun Jang

IPC: H01L27/11573 ,  H01L27/11582 ,  H01L23/528 ,  H01L29/417

Abstract: A semiconductor device includes first and second substrates including cell and peripheral circuit regions, first and second gate electrode structures, first and second channels, and first to third transistors. The first and second gate electrode structures include first and second gate electrodes in a vertical direction. The first and second channel extend through the first and second gate electrode structures. The first transistor is on the peripheral circuit region. The second gate electrode structure is on the first gate electrode structure and the first transistor. The second and third transistors are on the second gate electrode structure. The second substrate is on the second and third transistors. The first and second channels do not directly contact each other, are electrically connected with each other, and receive electrical signals from the second transistor. The first and third transistors apply electrical signals to the first and second gate electrode structures.

公开(公告)号：US20240339403A1

公开(公告)日：2024-10-10

申请号：US18405362

申请日：2024-01-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Moorym Choi ,  Taeyong Kim ,  Sunil Shim ,  Minhee Lee ,  Yunsun Jang ,  Hayoung Jeong

IPC: H01L23/528 ,  H01L23/522 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00

CPC classification number: H01L23/5283 ,  H01L23/5226 ,  H01L25/0652 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00 ,  H01L2225/06506

Abstract: A semiconductor device includes a first semiconductor structure including a first substrate, and a lower bonding structure on the first substrate, and a second semiconductor structure including a second substrate, and an upper bonding structure bonded to the lower bonding structure. The second semiconductor structure includes via patterns on the second substrate, a source contact pad including a material different from that of the second substrate, a source contact plug electrically connected to the source contact pad, a source contact via on the source contact pad, and an interconnection line that electrically connects the via patterns to the source contact plug. Lower surfaces of the via patterns are farther from the first substrate than a lower surface of the source contact via, and an upper surface of the second substrate is farther from the first substrate than an upper surface of the source contact pad.

公开(公告)号：US20240334716A1

公开(公告)日：2024-10-03

申请号：US18417970

申请日：2024-01-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Moorym Choi ,  Seungwoo Paek ,  Sunil Shim ,  Yunsun Jang

IPC: H10B80/00 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H10B80/00 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/80006 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A semiconductor device includes a first semiconductor structure including circuit elements on a first substrate, a lower interconnection structure on the circuit elements, and a lower bonding structure on the lower interconnection structure; and a second semiconductor structure including a second substrate on the first semiconductor structure, separation insulating patterns separating the second substrate, and disposed to be spaced apart from each other, gate electrodes stacked to be spaced apart from each other, separation regions passing through the gate electrodes, and disposed to be spaced apart from each other, channel structures passing through the gate electrodes, an upper interconnection structure below the gate electrodes, and an upper bonding structure bonded to the lower bonding structure, wherein the separation insulating patterns include first separation insulating patterns on the separation regions, and second separation insulating patterns between the channel structures and passing through the second substrate.