Abstract:
A semiconductor device includes: a data sampler configured to receive a data signal having a first frequency and to sample the data signal with a clock signal having a second frequency, higher than the first frequency, to output data for a time corresponding to a unit interval of the data signal; an error sampler configured to sample the data signal with an error clock signal having the second frequency and a phase, different from a phase of the clock signal, to output a plurality of pieces of error data for the time corresponding to the unit interval; and an eye-opening monitor (EOM) circuit configured to compare the data with each of the plurality of pieces of error data to obtain an eye diagram of the data signal in the unit interval.
Abstract:
An electronic device according to various embodiments of the present invention may comprise: a display; a communication module; a memory; and a processor electrically connected to the display, the communication module, and the memory, wherein the processor: receives, through the communication module, video data including at least one image frame and sensor data including at least one sensor value from a first external electronic device, outputs, through the display, a user interface for visually displaying the at least one sensor value; determines one of the at least one sensor value on the basis of a first user input; changes the determined sensor value on the basis of a second user input; and outputs, through the display, at least one image frame corresponding to the determined sensor value, according to the changed sensor value. Various other embodiments are possible.
Abstract:
A clock data recovery circuit includes a bang bang phase detector receiving data and a clock signal and determining whether a phase of the clock signal leads or lags a phase of the data, a digital loop filter receiving an output of the bang bang phase detector and filtering input jitter, an accumulator accumulating an output from the digital loop filter, an encoder encoding an output of the accumulator to generate a phase interpolation code, and a phase interpolator configured to generate the clock signal with an output phase in accordance with the phase interpolation code. The digital loop filter comprises a first sigma delta modulation (SDM) arithmetic block circuit connected to the bang bang phase detector.
Abstract:
An electronic device based on optical object recognition and a method of controlling the electronic device. The method of operating an optical object recognition-based an electronic device includes: executing an optical recognition function; recognizing an object outside the electronic device, via and optical sensor; searching for an Internet of Things (IoT) target device related to the recognized object; recommending an IoT action related to the recognized object; automatically preparing for and executing the IoT action; and performing voice feedback regarding the IoT action and the IoT target device.
Abstract:
An electronic device is disclosed. In addition, various embodiments identified through the specification are possible. The electronic device includes a display, a processor, and a memory storing instructions that, when executed by the processor, cause the processor to display, when a video supporting a plurality of orientation regions is played, a first screen corresponding to a first orientation region among the plurality of orientation regions, display a timeline representing a playback time of the video, display thumbnails of screens corresponding to the plurality of orientation regions at the first time point in response to a first user input pointing a first time point in the timeline, and receive a second user input scrolling the thumbnails.
Abstract:
An embodiment relates to an electronic device for synthesizing a two-dimensional object with a three-dimensional object. The electronic device may comprise a display, a memory, and at least one processor electrically connected to the display and the memory, wherein the processor may be configured to: control the display to display a three-dimensional object, at least one two-dimensional object, and at least one first button corresponding to the at least one two-dimensional object; in response to an input for selection of the at least one first button, associate the at least one two-dimensional object with a part of the three-dimensional object so that the at least one two-dimensional object moves in response to movement of the part of the three-dimensional object; and generate a first synthetic image including the three-dimensional object and the at least one two-dimensional object associated with the part of the three-dimensional object.
Abstract:
A clock data recovery circuit includes a bang bang phase detector receiving data and a clock signal and determining whether a phase of the clock signal leads or lags a phase of the data, a digital loop filter receiving an output of the bang bang phase detector and filtering input jitter, an accumulator accumulating an output from the digital loop filter, an encoder encoding an output of the accumulator to generate a phase interpolation code, and a phase interpolator configured to generate the clock signal with an output phase in accordance with the phase interpolation code. The digital loop filter comprises a first sigma delta modulation (SDM) arithmetic block circuit connected to the bang bang phase detector.
Abstract:
An apparatus for generating an output signal having a waveform that is repeated every period, includes a storage configured to store values corresponding to the waveform in a portion of a period of the output signal, a counter configured to generate a first index of a sample included in the output signal, a controller configured to generate at least one control signal based on the first index and the period of the output signal, and a calculation circuit configured to generate the output signal by calculating an output from the storage based on the at least one control signal.