公开(公告)号：US20150294969A1

公开(公告)日：2015-10-15

申请号：US14253439

申请日：2014-04-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jin-Wook Lee ,  Kang-III Seo

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L29/0692 ,  H01L29/66795 ,  H01L29/7855 ,  H01L29/7856

Abstract: A semiconductor device is provided. A substrate includes first and second active fins disposed in a row along a first direction. The first and second active fins are spaced apart from each other. A first dummy gate and a second dummy gate are disposed on the substrate and are extended in a second direction intersecting the first direction. The first dummy gate covers an end portion of the first active fin. The second dummy gate covers an end portion of the second active fin facing the end portion of the first active fin. A first dummy spacer is disposed on a sidewall of the first dummy gate. A second dummy spacer is disposed on a sidewall of the second dummy gate. The sidewall of the second dummy gate faces the sidewall of the first dummy gate. The first dummy spacer is in contact with the second dummy spacer.

Abstract translation: 提供半导体器件。 衬底包括沿着第一方向排成一排的第一和第二活性鳍。 第一和第二活动翅片彼此间隔开。 第一伪栅极和第二伪栅极设置在基板上并沿与第一方向相交的第二方向延伸。 第一伪栅极覆盖第一有源鳍片的端部。 第二伪栅极覆盖面向第一有源鳍片的端部的第二有源鳍片的端部。 第一虚拟间隔物设置在第一伪栅极的侧壁上。 第二虚拟间隔物设置在第二虚拟栅极的侧壁上。 第二伪栅极的侧壁面向第一虚拟栅极的侧壁。 第一假间隔件与第二假间隔件接触。

公开(公告)号：US20250107247A1

公开(公告)日：2025-03-27

申请号：US18595486

申请日：2024-03-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keumseok Park ,  Kang-III Seo

IPC: H01L27/02 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/786

Abstract: A method of forming an integrated circuit device includes providing a stacked transistor structure on a substrate. The stacked transistor structure includes a first channel pattern of a first transistor and a second channel pattern of a second transistor stacked on the first channel pattern. Second source/drain regions of the second transistor are formed at opposing ends of the second channel pattern, and an oxidation process is performed to oxidize upper and lower surfaces of the second source/drain regions and side surfaces of the first channel. First source/drain regions of the first transistor are then formed at opposing ends of the first channel pattern. Related devices and fabrication methods are also discussed.

公开(公告)号：US20160190128A1

公开(公告)日：2016-06-30

申请号：US14583252

申请日：2014-12-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Dae Suk ,  Kang-III Seo

IPC: H01L27/088 ,  H01L21/225 ,  H01L21/306 ,  H01L29/417 ,  H01L29/78 ,  H01L29/08 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66 ,  H01L21/308

CPC classification number: H01L27/0886 ,  H01L21/225 ,  H01L21/76805 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/485 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor device includes a fin type active pattern extended in a first direction and disposed on a substrate. A first gate electrode and a second gate electrode are disposed on the fin type active pattern. The first gate electrode and the second gate electrode are extended in a second direction crossing the first direction. A trench region is disposed in the fin type active pattern and between the first gate electrode and the second gate electrode. A source/drain region is disposed on a surface of the trench region. A source/drain contact is disposed on the source/drain region. The source/drain contact includes a first insulating layer disposed on the source/drain region and a metal oxide layer disposed on the first insulating layer.

Abstract translation: 半导体器件包括在第一方向上延伸并设置在衬底上的鳍式有源图案。 第一栅电极和第二栅电极设置在鳍型活性图案上。 第一栅电极和第二栅电极沿与第一方向交叉的第二方向延伸。 沟槽区域设置在翅片型有源图案中，并且位于第一栅极电极和第二栅极电极之间。 源极/漏极区域设置在沟槽区域的表面上。 源极/漏极触点设置在源极/漏极区域上。 源极/漏极接触包括设置在源极/漏极区域上的第一绝缘层和设置在第一绝缘层上的金属氧化物层。