公开(公告)号：US20240332131A1

公开(公告)日：2024-10-03

申请号：US18448482

申请日：2023-08-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： JINTAE KIM ,  Keumseok Park ,  Kang-Ill Seo

IPC: H01L23/48 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/088 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L23/481 ,  H01L21/823412 ,  H01L21/823418 ,  H01L27/0688 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: Integrated circuit devices may include a power switch cell including an upper transistor on a substrate and a lower transistor between the substrate and the upper transistor. The upper transistor may include an upper channel region, first and second upper source/drain regions, and an upper gate electrode on the upper channel region. The lower transistor may include a lower channel region, first and second lower source/drain regions, and a lower gate electrode on the lower channel region. The first and second upper source/drain regions and the first and second lower source/drain regions may have the same conductivity type, the first upper source/drain region and the first lower source/drain region may be electrically connected to each other, the second upper source/drain region and the second lower source/drain region may be electrically connected to each other, and the upper and lower gate electrodes may be electrically connected to each other.

公开(公告)号：US20240304669A1

公开(公告)日：2024-09-12

申请号：US18233693

申请日：2023-08-14

Applicant: SAMSUNG ELECTRONICS CO., Ltd.

Inventor： Keumseok Park ,  Myung Yang ,  Kang-ill Seo

IPC: H01L29/08 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/088 ,  H01L29/06 ,  H01L29/36 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/0847 ,  H01L21/823418 ,  H01L27/0688 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/36 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: Provided is a three-dimensional field-effect transistor (3DSFET) device including: a 1st source/drain region; and a 2nd source/drain region stacked on the 1st source/drain region, wherein the 1st source/drain region has a protrusion at a 2nd upper corner portion among a 1st upper corner portion and the 2nd upper corner portion opposite to each other in a channel-width direction view.

公开(公告)号：US20230395659A1

公开(公告)日：2023-12-07

申请号：US17934533

申请日：2022-09-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keumseok Park ,  Jaejik Baek ,  Kang-ill Seo

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/786 ,  H01L29/08 ,  H01L25/11 ,  H01L21/8234

CPC classification number: H01L29/0673 ,  H01L29/6656 ,  H01L29/78696 ,  H01L29/0847 ,  H01L25/117 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823468

Abstract: Transistor devices are provided. A transistor device includes a transistor stack including first and second transistors. The transistor device includes an insulating spacer that is on a sidewall of a first gate of the first transistor and between a plurality of first semiconductor channel layers of the first transistor. Moreover, the transistor device includes a semiconductor spacer that is on a sidewall of a second gate of the second transistor and between a plurality of second semiconductor channel layers of the second transistor. Related methods of forming transistor devices are also provided.

公开(公告)号：US09837500B2

公开(公告)日：2017-12-05

申请号：US15002379

申请日：2016-01-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunjung Lee ,  Keumseok Park ,  Jinyeong Joe ,  Yong-Suk Tak

IPC: H01L29/417 ,  H01L23/535 ,  H01L29/78

CPC classification number: H01L29/41791 ,  H01L29/785

Abstract: Provided is a semiconductor device. In some examples, the semiconductor device includes an fin active region protruding from a substrate, gate patterns disposed on the fin active region, a source/drain region disposed on the fin active region between the gate patterns, and contact patterns disposed on the source/drain region. The source/drain region may have a protruding middle section, which may form a wave-shaped upper surface of the source/drain region.

公开(公告)号：US20250040242A1

公开(公告)日：2025-01-30

申请号：US18521323

申请日：2023-11-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Keumseok Park ,  Seungchan Yun ,  Kang-ill Seo

IPC: H01L27/092 ,  H01L21/822 ,  H01L21/8238 ,  H01L23/528 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

Abstract: Provided is a semiconductor device which includes: a 1st source/drain region connected to a 1st channel structure which is controlled by a 1st gate structure; a 2nd source/drain region, above the 1st source/drain region, connected to a 2nd channel structure which is controlled by a 2nd gate structure; and a middle isolation structure between the 1st gate structure and the 2nd gate structure, wherein the middle isolation structure comprises two or more vertically-stacked semiconductor layers.

公开(公告)号：US20240072048A1

公开(公告)日：2024-02-29

申请号：US18184901

申请日：2023-03-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungchan Yun ,  Seungmin Song ,  Myunghoon Jung ,  Keumseok Park ,  Kang-ill Seo

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L27/088 ,  H01L21/823412 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/775 ,  H01L29/78696

Abstract: An integrated circuit device may comprise an upper transistor that is on a substrate. The upper transistor may comprise an upper channel region. The integrated circuit device may further comprise a lower transistor that is between the substrate and the upper transistor. The lower transistor may comprise a lower channel region. The integrated circuit device may further include an integrated insulator that is between the lower channel region and the upper channel region. The integrated insulator may comprise an outer layer and an inner layer in the outer layer, wherein the inner layer and the outer layer comprise different materials.

公开(公告)号：US20250107247A1

公开(公告)日：2025-03-27

申请号：US18595486

申请日：2024-03-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keumseok Park ,  Kang-III Seo

IPC: H01L27/02 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/786

Abstract: A method of forming an integrated circuit device includes providing a stacked transistor structure on a substrate. The stacked transistor structure includes a first channel pattern of a first transistor and a second channel pattern of a second transistor stacked on the first channel pattern. Second source/drain regions of the second transistor are formed at opposing ends of the second channel pattern, and an oxidation process is performed to oxidize upper and lower surfaces of the second source/drain regions and side surfaces of the first channel. First source/drain regions of the first transistor are then formed at opposing ends of the first channel pattern. Related devices and fabrication methods are also discussed.

公开(公告)号：US20250081562A1

公开(公告)日：2025-03-06

申请号：US18434263

申请日：2024-02-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keumseok Park ,  Kang-ill Seo

IPC: H01L29/10 ,  H01L21/74 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

Abstract: Provided is a semiconductor device which includes: a substrate; a 1st source/drain region above the substrate; and an under-blocking layer below the 1st source/drain region, wherein the under-blocking layer faces the substrate, and comprises one or more insulation materials, wherein the under-blocking layer is disposed below a level of a top surface of the substrate.

公开(公告)号：US20240290689A1

公开(公告)日：2024-08-29

申请号：US18215985

申请日：2023-06-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungchan YUN ,  Wonhyuk Hong ,  Keumseok Park ,  Se Jung Park ,  Kang-ill Seo

IPC: H01L23/48 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L23/481 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: Provided is a semiconductor device including: a channel structure; source/drain regions connected by the channel structure; and a backside contact structure formed below at least one of the source/drain region, wherein, in a 1st-direction cross section view, a width of an upper portion of the backside contact structure close to the source/drain region is smaller than a width of a lower portion of the backside contact structure distant from the source/drain region, wherein, in a 2nd-direction cross-section view, widths of the upper portion and the lower portion of the backside contact structure are substantially uniform along a vertical downward direction, and wherein the 1st direction intersects the 2nd direction.