公开(公告)号：US09666706B2

公开(公告)日：2017-05-30

申请号：US15210368

申请日：2016-07-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-jin Cho ,  Kyoung-yeon Kim ,  Sang-moon Lee ,  Ki-ha Hong ,  Eui-chul Hwang

IPC: H01L21/336 ,  H01L29/778 ,  H01L29/66 ,  H01L29/20 ,  H01L29/78 ,  H01L21/02 ,  H01L29/12 ,  H01L29/423 ,  H01L29/15 ,  H01L29/205

CPC classification number: H01L29/7784 ,  H01L21/02538 ,  H01L29/122 ,  H01L29/127 ,  H01L29/158 ,  H01L29/20 ,  H01L29/205 ,  H01L29/42376 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/66522 ,  H01L29/66795 ,  H01L29/7783 ,  H01L29/7787 ,  H01L29/785

Abstract: A semiconductor device including a group III-V barrier and a method of manufacturing the semiconductor device, the semiconductor device including: a substrate, insulation layers formed to be spaced apart on the substrate, a group III-V material layer for filling the space between the insulation layers and having a portion protruding higher than the insulation layers, a barrier layer for covering the side and upper surfaces of the protruding portion of the group III-V material layer and having a bandgap larger than that of the group III-V material layer, a gate insulation film for covering the surface of the barrier layer, a gate electrode formed on the gate insulation film, and source and drain electrodes formed apart from the gate electrode. The overall composition of the group III-V material layer is uniform. The barrier layer may include a group III-V material for forming a quantum well.

公开(公告)号：US08791515B2

公开(公告)日：2014-07-29

申请号：US13915272

申请日：2013-06-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki-ha Hong ,  Jong-seob Kim ,  Jai-Kwang Shin

IPC: H01L29/66 ,  H01L29/82 ,  H01L29/94

CPC classification number: H01L29/66984 ,  B82Y25/00 ,  H01F1/401 ,  H01F10/1936 ,  H01F10/3254

Abstract: Provided are spin field effect logic devices, the logic devices including: a gate electrode; a channel formed of a magnetic material above the gate electrode to selectively transmit spin-polarized electrons; a source on the channel; and a drain and an output electrode on the channel outputting electrons transmitted from the source. The gate electrode may control a magnetization state of the channel in order to selectively transmit the electrons injected from the source to the channel.

Abstract translation: 提供的是自旋场效应逻辑器件，逻辑器件包括：栅电极; 由栅电极上方的磁性材料形成的沟道，以选择性地透射自旋极化电子; 频道上的来源; 以及沟道上的漏极和输出电极，输出从源极发射的电子。 栅电极可以控制通道的磁化状态，以选择性地将从源引入的电子传输到通道。

公开(公告)号：US09859410B2

公开(公告)日：2018-01-02

申请号：US14497585

申请日：2014-09-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： In-jun Hwang ,  Jai-kwang Shin ,  Jae-joon Oh ,  Jong-seob Kim ,  Hyuk-soon Choi ,  Ki-ha Hong

IPC: H01L29/778 ,  H01L29/267 ,  H01L29/51 ,  H01L29/66 ,  H01L29/08 ,  H01L29/10 ,  H01L29/20 ,  H01L29/423

CPC classification number: H01L29/778 ,  H01L29/0847 ,  H01L29/1029 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/267 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/517 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7785 ,  H01L29/7786

Abstract: A High electron mobility transistor (HEMT) includes a source electrode, a gate electrode, a drain electrode, a channel forming layer in which a two-dimensional electron gas (2DEG) channel is induced, and a channel supplying layer for inducing the 2DEG channel in the channel forming layer. The source electrode and the drain electrode are located on the channel supplying layer. A channel increase layer is between the channel supplying layer and the source and drain electrodes. A thickness of the channel supplying layer is less than about 15 nm.

公开(公告)号：US09299800B2

公开(公告)日：2016-03-29

申请号：US14687488

申请日：2015-04-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyuk-soon Choi ,  Jung-hee Lee ,  Jai-kwang Shin ,  Jae-joon Oh ,  Jong-bong Ha ,  Jong-seob Kim ,  In-jun Hwang ,  Ki-ha Hong ,  Ki-sik Im ,  Ki-won Kim ,  Dong-seok Kim

IPC: H01L29/66 ,  H01L21/762 ,  H01L29/08 ,  H01L29/20 ,  H01L29/423 ,  H01L29/778 ,  H01L21/02 ,  H01L29/201 ,  H01L29/205 ,  H01L29/207

CPC classification number: H01L29/66462 ,  H01L21/0254 ,  H01L21/76237 ,  H01L29/0847 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/207 ,  H01L29/4236 ,  H01L29/7787

Abstract: The methods may include forming a first material layer on a substrate, increasing electric resistance of the first material layer, and forming a source pattern and a drain pattern, which are spaced apart from each other, on the first material layer, a band gap of the source and drain patterns greater than a band gap of a first material layer.

Abstract translation: 所述方法可以包括在衬底上形成第一材料层，增加第一材料层的电阻，以及在第一材料层上形成彼此间隔开的源图案和漏极图案，带隙为 源极和漏极图案大于第一材料层的带隙。

公开(公告)号：US20150221745A1

公开(公告)日：2015-08-06

申请号：US14686436

申请日：2015-04-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： In-jun HWANG ,  Hyuk-soon Choi ,  Jae-joon Oh ,  Jong-bong Ha ,  Jong-seob Kim ,  Ki-ha Hong ,  Jai-kwang Shin

IPC: H01L29/66 ,  H01L29/20

CPC classification number: H01L29/66462 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/7787

Abstract: High electron mobility transistors (HEMTs) including a substrate and a HEMT stack on the substrate, the HEMT stack including a compound semiconductor layer that includes a 2-dimensional electron gas (2DEG), an upper compound semiconductor layer that has a polarization index higher than a polarization index of the compound semiconductor layer, and a source electrode, a drain electrode, and a gate that are disposed on the upper compound semiconductor layer. The substrate may be a nitride substrate that has a dielectric constant and a thermal conductivity higher than a dielectric constant and a thermal conductivity of a silicon substrate. The substrate may include an insulating layer that has a dielectric constant and a thermal conductivity higher than a dielectric constant and a thermal conductivity of the silicon substrate, a metal layer that is deposited on the insulating layer, and a plate that is attached to the metal layer.

Abstract translation: 包括衬底和衬底上的HEMT堆叠的高电子迁移率晶体管（HEMT），所述HEMT堆叠包括包含二维电子气（2DEG）的化合物半导体层，具有高于 化合物半导体层的极化指数，以及设置在上部化合物半导体层上的源电极，漏电极和栅极。 衬底可以是氮化物衬底，其具有高于介电常数和硅衬底的热导率的介电常数和导热系数。 衬底可以包括绝缘层，该绝缘层的介电常数和热导率高于介电常数和硅衬底的热导率，沉积在绝缘层上的金属层和附着到金属的板 层。