公开(公告)号：US20240064996A1

公开(公告)日：2024-02-22

申请号：US18170136

申请日：2023-02-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kiheun Lee ,  Yongseok Kim ,  Hyuncheol Kim ,  Ilho Myeong ,  Daewon Ha

IPC: H10B51/20 ,  H10B51/10 ,  H01L23/528 ,  H01L29/51 ,  H01L29/78

CPC classification number: H10B51/20 ,  H10B51/10 ,  H01L23/5283 ,  H01L29/516 ,  H01L29/78391

Abstract: A semiconductor device includes first and second cell arrays. The first cell array includes a first gate electrode that extends in a vertical direction, a first channel pattern on a side surface of the first gate electrode, and a first bit line electrically connected to the first channel pattern. The second cell array includes a second gate electrode that extends in the vertical direction, a second channel pattern on a side surface of the second gate electrode, and a second bit line electrically connected to the second channel pattern. A first bit line pad is electrically connected to the first bit line and a second bit line pad is electrically connected to the second bit line. The first bit line pad is spaced apart from the second bit line pad with the first and second cell arrays therebetween.

公开(公告)号：US20230309317A1

公开(公告)日：2023-09-28

申请号：US18059010

申请日：2022-11-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyuncheol KIM ,  Yongseok Kim ,  Kiheun Lee ,  Sangkil Lee ,  Daewon Ha

IPC: H10B53/20 ,  H10B53/10 ,  H01L23/528

CPC classification number: H01L27/11514 ,  H01L27/11504 ,  H01L23/5283

Abstract: A semiconductor memory device is provided. The semiconductor memory device may include a semiconductor substrate; a data storage layer including capacitors disposed on the semiconductor substrate; a switching element layer on the data storage layer and including transistors connected to the respective capacitors; and a wiring layer on the switching element layer and including bit lines connected to the transistors, The respective transistors include an active pattern, a word line that crosses the active pattern such that the word line surrounds a first sidewall, a second sidewall and a top surface of the active pattern, and a ferroelectric layer between the word line and the active patter.

公开(公告)号：US20230371269A1

公开(公告)日：2023-11-16

申请号：US18195522

申请日：2023-05-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyuncheol Kim ,  Yongseok Kim ,  Kiheun Lee ,  Daewon Ha

IPC: H10B51/30 ,  H10B51/10 ,  H01L29/78 ,  H01L21/28

CPC classification number: H10B51/30 ,  H01L29/40111 ,  H01L29/78391 ,  H10B51/10

Abstract: A memory device includes a channel region, a conductive electrode on the channel region, and a data storage structure between the channel region and the conductive electrode. The data storage structure includes a stack structure including two-dimensional material layers and ferroelectric layers stacked alternately and repeatedly in a direction perpendicular to a surface of the channel region. A thickness of each of the ferroelectric layers is greater than a thickness of each of the two-dimensional material layers.