公开(公告)号：US20180108674A1

公开(公告)日：2018-04-19

申请号：US15832384

申请日：2017-12-05

申请人： SK hynix Inc.

发明人： Nam Jae LEE

IPC分类号： H01L21/768 ,  H01L23/528 ,  H01L23/522 ,  H01L29/417

CPC分类号： H01L27/11582 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/11504 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/41741

摘要： A semiconductor device includes bit lines extending along a first direction, the bit lines being arranged along a second direction intersecting the first direction, a plurality of channel layers disposed under the bit lines, the plurality of channel layers extending in a third direction perpendicular to a plane extending along the first and second directions and spaced apart along the second direction, so that each channel layer is at least partially overlapped with at least two of the bit lines, and a contact plug extending, from the channel layer, toward one of the bit lines overlapped with the channel layer.

公开(公告)号：US20170200733A1

公开(公告)日：2017-07-13

申请号：US15170558

申请日：2016-06-01

申请人： SK hynix Inc.

发明人： Nam Jae LEE

IPC分类号： H01L27/115 ,  H01L23/528 ,  H01L21/768 ,  H01L23/522

CPC分类号： H01L27/11582 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/11504 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/41741

摘要： A semiconductor device includes bit lines extending along a first direction, the bit lines being arranged along a second direction intersecting the first direction, a plurality of channel layers disposed under the bit lines, the plurality of channel layers extending in a third direction perpendicular to a plane extending along the first and second directions and spaced apart along the second direction, so that each channel layer is at least partially overlapped with at least two of the bit lines, and a contact plug extending, from the channel layer, toward one of the bit lines overlapped with the channel layer.

公开(公告)号：US09508730B2

公开(公告)日：2016-11-29

申请号：US14734140

申请日：2015-06-09

申请人： SK hynix Inc.

发明人： Ki Hong Lee ,  Seung Ho Pyi

IPC分类号： H01L27/115 ,  H01L27/24

CPC分类号： H01L27/11504 ,  H01L27/11507 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/2436 ,  H01L27/2454 ,  H01L27/2481 ,  H01L27/249 ,  H01L45/04 ,  H01L45/06 ,  H01L45/10 ,  H01L45/1226 ,  H01L45/145 ,  H01L45/16

摘要： A semiconductor device includes a substrate in which a cell region and contact regions located at both sides of the cell region are defined, a first source layer formed over the substrate, a second source layer formed over the first source layer, a reinforcement pattern formed in the second source layer, a stacked structure including conductive layers and insulating layers alternately stacked over the second source layer and the reinforcement pattern, channel layers passing through the stacked structure and the second source layer and electrically coupled to the second source layer, and an isolation insulating pattern passing through at least one top conductive layer of the conductive layers.

摘要翻译： 一种半导体器件包括其中限定了单元区域和位于单元区域两侧的接触区域的基板，形成在基板上的第一源极层，形成在第一源极层上的第二源极层，形成在第一源极层 第二源极层，包括交替层叠在第二源极层和加强图案上的导电层和绝缘层的堆叠结构，穿过堆叠结构的沟道层和第二源极层，并且电耦合到第二源极层，以及隔离层 绝缘图案通过导电层的至少一个顶部导电层。

公开(公告)号：US20160268263A1

公开(公告)日：2016-09-15

申请号：US14734140

申请日：2015-06-09

申请人： SK hynix Inc.

发明人： Ki Hong LEE ,  Seung Ho PYI

IPC分类号： H01L27/115

CPC分类号： H01L27/11504 ,  H01L27/11507 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/2436 ,  H01L27/2454 ,  H01L27/2481 ,  H01L27/249 ,  H01L45/04 ,  H01L45/06 ,  H01L45/10 ,  H01L45/1226 ,  H01L45/145 ,  H01L45/16

摘要： A semiconductor device includes a substrate in which a cell region and contact regions located at both sides of the cell region are defined, a first source layer formed over the substrate, a second source layer formed over the first source layer, a reinforcement pattern formed in the second source layer, a stacked structure including conductive layers and insulating layers alternately stacked over the second source layer and the reinforcement pattern, channel layers passing through the stacked structure and the second source layer and electrically coupled to the second source layer, and an isolation insulating pattern passing through at least one top conductive layer of the conductive layers.

摘要翻译： 一种半导体器件包括其中限定了单元区域和位于单元区域两侧的接触区域的基板，形成在基板上的第一源极层，形成在第一源极层上的第二源极层，形成在第一源极层 第二源极层，包括交替层叠在第二源极层和加强图案上的导电层和绝缘层的堆叠结构，穿过堆叠结构的沟道层和第二源极层，并且电耦合到第二源极层，以及隔离层 绝缘图案通过导电层的至少一个顶部导电层。

公开(公告)号：US20160118404A1

公开(公告)日：2016-04-28

申请号：US14875744

申请日：2015-10-06

申请人： Haibing Peng

发明人： Haibing Peng

IPC分类号： H01L27/115 ,  H01L29/78 ,  H01L29/16 ,  H01L29/51

CPC分类号： H01L27/11597 ,  H01L27/11504 ,  H01L27/11507 ,  H01L27/11514 ,  H01L27/11587 ,  H01L27/1159 ,  H01L29/16 ,  H01L29/516 ,  H01L29/517 ,  H01L29/78391

摘要： The present invention provides a design of three-dimensional non-volatile ferroelectric random access memory (FeRAM) devices for increasing the storage density. The key components include: (1) FeRAM device structures with (i) field-effect-transistors electrically connected either in series or in parallel as a basic memory group and (ii) a double-gate structure for implementing read/write schemes with full random access to individual memory cells, where one type of gates employs ferroelectrics layers as the gate dielectrics while the other type of gates employs conventional dielectric materials as the gate dielectrics; and (2) FeRAM device structures with stacked ferroelectric-capacitors and field-effect-transistors electrically connected in series as a basic NAND memory group. Example fabrication processes for implementing such three-dimensional FeRAM devices are also provided.

摘要翻译： 本发明提供了一种用于提高存储密度的三维非易失性铁电随机存取存储器（FeRAM）器件的设计。 关键部件包括：（1）FeRAM器件结构，其中（i）场效应晶体管串联或并联电连接为基本存储器组，以及（ii）双栅结构，用于实现具有完整的读/写方案 随机访问单个存储器单元，其中一种类型的栅极使用铁电层作为栅极电介质，而另一种类型的栅极使用常规介电材料作为栅极电介质; 和（2）具有层叠铁电电容器和作为基本NAND存储器组串联电连接的场效应晶体管的FeRAM器件结构。 还提供了用于实现这种三维FeRAM器件的示例性制造工艺。

公开(公告)号：US20150262832A1

公开(公告)日：2015-09-17

申请号：US14479590

申请日：2014-09-08

申请人： Kabushiki Kaisha Toshiba

发明人： Keisuke KIKUTANI ,  Yuta WATANABE ,  Kazunori NISHIKAWA

IPC分类号： H01L21/308 ,  H01L21/3213 ,  H01L21/033

CPC分类号： H01L21/32139 ,  H01L21/02115 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/0337 ,  H01L21/31116 ,  H01L21/31122 ,  H01L27/11504 ,  H01L27/11529 ,  H01L27/11565 ,  H01L27/11573

摘要： In accordance with an embodiment, a manufacturing method of a semiconductor device includes manufacturing a mask pattern and forming an interconnection using the mask pattern. The manufacturing the mask pattern includes forming a first pattern of a first material, depositing a second material over the first pattern, forming a first sidewall film on sidewalls of the first pattern by a first etchback, depositing a third material over the first sidewall film, forming a second sidewall film on sidewalls of the first sidewall film by a second etchback, adjusting the first pattern and second sidewall film so as to have the same height, and selectively removing the first sidewall film. The first pattern has a line width of a first width equal to the thicknesses of the first and second sidewall films. The mask pattern includes a line-and-space having a line width and a space equal to the first width, respectively.

摘要翻译： 根据实施例，半导体器件的制造方法包括制造掩模图案并使用掩模图案形成互连。 制造掩模图案包括形成第一材料的第一图案，在第一图案上沉积第二材料，通过第一回蚀在第一图案的侧壁上形成第一侧壁膜，在第一侧壁膜上沉积第三材料， 通过第二回蚀在第一侧壁膜的侧壁上形成第二侧壁膜，调节第一图案和第二侧壁膜以具有相同的高度，以及选择性地去除第一侧壁膜。 第一图案具有等于第一和第二侧壁膜的厚度的第一宽度的线宽。 掩模图案包括分别具有线宽和等于第一宽度的空间的线和空间。

公开(公告)号：US08837194B2

公开(公告)日：2014-09-16

申请号：US13436151

申请日：2012-03-30

申请人： Yoshikazu Fujimori ,  Hiromitsu Kimura ,  Toshiyuki Kanaya ,  Daisuke Notsu

发明人： Yoshikazu Fujimori ,  Hiromitsu Kimura ,  Toshiyuki Kanaya ,  Daisuke Notsu

IPC分类号： G11C11/22 ,  H01L27/115 ,  H03K3/356 ,  H01L27/02 ,  H01L49/02

CPC分类号： G11C11/22 ,  G11C11/221 ,  H01L27/0207 ,  H01L27/11504 ,  H01L27/11507 ,  H01L27/11512 ,  H01L28/55 ,  H03K3/356008

摘要： A data holding device includes a loop structure unit configured to hold data using a plurality of logic gates connected in a loop shape, a nonvolatile storage unit including a plurality of ferroelectric elements, the nonvolatile storage unit configured to store the data held in the loop structure unit in a nonvolatile manner using hysteresis characteristics of the ferroelectric elements, and a circuit separation unit configured to electrically separate the loop structure unit and the nonvolatile storage unit. The ferroelectric elements of the nonvolatile storage unit are surrounded by a dummy element smaller in width than the ferroelectric elements.

摘要翻译： 数据保持装置包括：环路结构单元，被配置为使用以环形形式连接的多个逻辑门保存数据;非易失性存储单元，包括多个铁电元件;非易失性存储单元，被配置为存储保持在所述环路结构中的数据 使用铁电元件的滞后特性以非易失性方式单元，以及电路分离单元，其被配置为电气分离环路结构单元和非易失性存储单元。 非易失性存储单元的铁电元件被宽度小于铁电元件的虚拟元件围绕。

公开(公告)号：US08728901B2

公开(公告)日：2014-05-20

申请号：US14010134

申请日：2013-08-26

申请人： Cypress Semiconductor Corporation

发明人： Shan Sun ,  Thomas Davenport ,  John Cronin

IPC分类号： H01L21/20

CPC分类号： H01L27/11502 ,  H01L27/11504 ,  H01L28/55 ,  H01L28/90

摘要： A method for fabricating a non-volatile, ferroelectric random access memory (F-RAM) device is described. In one embodiment, the method includes forming an opening in an insulating layer over a surface of a substrate, and forming bottom electrode spacers proximal to sidewalls of the opening. Next, a ferroelectric dielectric layer is formed in the opening over the surface of the substrate and between the bottom electrode spacers, and a pair of top electrodes is formed within the opening comprising first and second side portions displaced laterally from respective ones of the bottom electrode spacers by the ferroelectric dielectric layer.

摘要翻译： 描述了制造非易失性铁电随机存取存储器（F-RAM）装置的方法。 在一个实施例中，该方法包括在衬底的表面上的绝缘层中形成开口，以及形成靠近开口侧壁的底部电极间隔件。 接下来，在基板的表面和底部电极间隔件之间的开口中形成铁电介质层，并且在该开口内形成一对顶部电极，该第一和第二侧面部分从底部电极 通过铁电介电层形成间隔物。

公开(公告)号：US20140093983A1

公开(公告)日：2014-04-03

申请号：US14010174

申请日：2013-08-26

申请人： CYPRESS SEMICONDUCTOR CORPORATION

发明人： John Cronin ,  Shan Sun ,  Tom E. Davenport

IPC分类号： H01L43/02 ,  H01L27/22

CPC分类号： H01L43/02 ,  H01L27/11504 ,  H01L27/11507 ,  H01L27/228

摘要： A method for a non-volatile, ferroelectric random access memory (F-RAM) device that includes a ferroelectric capacitor aligned with a preexisting structure is described. In one embodiment, the method includes forming an opening in an insulating layer over a contact in a planar surface of a substrate to expose at least a portion of the contact. Next a self-aligned contact (SAC) is formed electrically coupling to the contact, the SAC medially located in the opening and proximal to a sidewall thereof. A ferroelectric spacer is then formed in the opening medially of the SAC, and a top electrode spacer formed in the opening over the insulating cap and medially of the ferroelectric spacer.

摘要翻译： 描述了一种包括与预先存在的结构对准的铁电电容器的非易失性铁电随机存取存储器（F-RAM）器件的方法。 在一个实施例中，该方法包括在基板的平坦表面中的接触件上方的绝缘层中形成开口，以暴露接触件的至少一部分。 接下来，自对准接触（SAC）形成为电耦合到接触件，SAC内侧位于开口中并且靠近其侧壁。 然后在SAC的中间的开口中形成铁电间隔物，以及形成在绝缘帽上的开口中的顶部电极间隔物，并且在铁电间隔物的中间。

公开(公告)号：US20120168837A1

公开(公告)日：2012-07-05

申请号：US13312352

申请日：2011-12-06

申请人： Steven Craig BARTLING ,  Michael Patrick CLINTON ,  Borna OBRADOVIC

发明人： Steven Craig BARTLING ,  Michael Patrick CLINTON ,  Borna OBRADOVIC

IPC分类号： H01L27/115 ,  H01L21/8246

CPC分类号： H01L27/11507 ,  H01L27/0207 ,  H01L27/11504 ,  H01L28/55

摘要： A ferroelectric apparatus includes a circuit having a first capacitor electrically coupled to a plate line via a top terminal connection of the first ferroelectric capacitor and to a storage node via a bottom terminal connection of the first ferroelectric capacitor. The circuit also includes a second ferroelectric capacitor electrically coupled to a second plate line via a second bottom terminal connection of the second ferroelectric capacitor and to the storage node via a second top terminal connection of the second ferroelectric capacitor.

摘要翻译： 铁电设备包括电路，该电路具有经由第一铁电电容器的顶端连接器电连接到板线的第一电容器和经由第一铁电电容器的底端连接而连接到存储节点的电路。 电路还包括经由第二铁电电容器的第二底部端子连接电耦合到第二板线的第二铁电电容器和经由第二铁电电容器的第二顶部端子连接到存储节点的第二铁电电容器。