公开(公告)号：US20220216193A1

公开(公告)日：2022-07-07

申请号：US17704260

申请日：2022-03-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kil-soo KIM

IPC: H01L25/18 ,  H01L25/065 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00

Abstract: A semiconductor package includes a package substrate, a processor chip mounted on a first region of the package substrate, a plurality of memory chips mounted on a second region of the package substrate being spaced apart from the first region of the package substrate, a signal transmission device mounted on a third region of the package substrate between the first and second regions of the package substrate, and a plurality of first bonding wires connecting the plurality of memory chips to the signal transmission device. The signal transmission device includes upper pads connected to the plurality of first bonding wires, penetrating electrodes arranged in a main body portion of the signal transmission device and connected to the upper pads, and lower pads in a lower surface portion of the signal transmission device and connected to the penetrating electrodes and connected to the package substrate via bonding balls.

公开(公告)号：US20200343219A1

公开(公告)日：2020-10-29

申请号：US16923418

申请日：2020-07-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yong-hoon KIM ,  Kil-soo KIM ,  Kyung-suk OH ,  Tae-joo HWANG

IPC: H01L25/065 ,  H01L23/552 ,  H01L23/367 ,  H04M1/02

Abstract: An electronic device includes a circuit board, a semiconductor device package mounted on the circuit board, the semiconductor device package including a package substrate connected to the circuit board, a first semiconductor device and a second semiconductor device mounted side by side on the package substrate, and a molding surrounding a sidewall of the first semiconductor device and a sidewall of the second semiconductor device, the molding not covering a top surface of the first semiconductor device, and a heat dissipation structure on the semiconductor device package, the top surface of the first semiconductor device being in contact with the heat dissipation structure.

公开(公告)号：US20130082368A1

公开(公告)日：2013-04-04

申请号：US13632215

申请日：2012-10-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae-hoon KIM ,  Young-lyong KIM ,  Hyeong-seob KIM ,  Kil-soo KIM

IPC: H01L23/552

CPC classification number: H01L23/552 ,  H01L23/295 ,  H01L23/3121 ,  H01L23/3135 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12044 ,  H01L2924/1815 ,  H01L2924/00 ,  H01L2224/0401

Abstract: An EMI shielded semiconductor package includes a semiconductor package and an EMI shield layer formed on at least a part of a surface of the EMI shielded semiconductor package. The EMI shield layer includes a matrix layer; a metal layer positioned on the matrix layer; and a first seed particle positioned in an interface between the matrix layer and the metal layer. Unlike a conventional shielding process that is performed for a device level, a shielding process may be performed for a mounting substrate level, and thus the semiconductor package and the substrate module may be manufactured with high-productivity at low costs in a short period of time.

Abstract translation: EMI屏蔽半导体封装包括形成在EMI屏蔽半导体封装的表面的至少一部分上的半导体封装和EMI屏蔽层。 EMI屏蔽层包括矩阵层; 位于基体层上的金属层; 以及位于基质层和金属层之间的界面中的第一种子颗粒。 与针对器件级别执行的常规屏蔽处理不同，可以对安装衬底级别执行屏蔽工艺，因此半导体封装和衬底模块可以在短时间内以低成本生产高生产率 。

公开(公告)号：US20190295917A1

公开(公告)日：2019-09-26

申请号：US16190825

申请日：2018-11-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kil-soo KIM ,  Yong-hoon KIM ,  Hyun-ki KIM ,  Kyung-suk OH

IPC: H01L23/367 ,  H01L23/31 ,  H01L25/065 ,  H01L23/552 ,  H01L23/00

Abstract: A semiconductor package includes a package substrate, a lower semiconductor chip on the package substrate, a heat emission member on the lower semiconductor chip, the heat emission member having a horizontal unit and a vertical unit connected to the horizontal unit, a first semiconductor chip stack and a second semiconductor chip stack on the horizontal unit, and a molding member that surrounds the lower semiconductor chip, the first and second semiconductor chip stacks, and the heat emission member. The vertical unit may be arranged between the first semiconductor chip stack and the second semiconductor chip stack, and an upper surface of the vertical unit may be exposed in the molding member.

公开(公告)号：US20190148349A1

公开(公告)日：2019-05-16

申请号：US16051926

申请日：2018-08-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kil-soo KIM

IPC: H01L25/18 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065 ,  H01L23/31

Abstract: A semiconductor package includes a package substrate, a processor chip mounted on a first region of the package substrate, a plurality of memory chips mounted on a second region of the package substrate being spaced apart from the first region of the package substrate, a signal transmission device mounted on a third region of the package substrate between the first and second regions of the package substrate, and a plurality of first bonding wires connecting the plurality of memory chips to the signal transmission device. The signal transmission device includes upper pads connected to the plurality of first bonding wires, penetrating electrodes arranged in a main body portion of the signal transmission device and connected to the upper pads, and lower pads in a lower surface portion of the signal transmission device and connected to the penetrating electrodes and connected to the package substrate via bonding balls.

公开(公告)号：US20190148337A1

公开(公告)日：2019-05-16

申请号：US16002018

申请日：2018-06-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-hoon KIM ,  Kil-soo KIM ,  Kyung-suk OH ,  Tae-joo HWANG

IPC: H01L25/065 ,  H01L23/552 ,  H01L23/367

Abstract: An electronic device includes a circuit board, a semiconductor device package mounted on the circuit board, the semiconductor device package including a package substrate connected to the circuit board, a first semiconductor device and a second semiconductor device mounted side by side on the package substrate, and a molding surrounding a sidewall of the first semiconductor device and a sidewall of the second semiconductor device, the molding not covering a top surface of the first semiconductor device, and a heat dissipation structure on the semiconductor device package, the top surface of the first semiconductor device being in contact with the heat dissipation structure.