公开(公告)号：US20200035796A1

公开(公告)日：2020-01-30

申请号：US16404857

申请日：2019-05-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chang-yeon LEE ,  Jin-wook LEE ,  Min-chan GWAK ,  Kye-Hyun BAEK ,  Hong-bae PARK

IPC: H01L29/417 ,  H01L27/088 ,  H01L29/78 ,  H01L21/8234

Abstract: An integrated circuit device including a substrate; a fin-type active region protruding from the substrate; a gate line intersecting the fin-type active region and covering a top surface and side walls thereof; a gate insulating capping layer covering the gate line; source/drain regions at sides of the gate line on the fin-type active region; first conductive plugs connected to the source/drain regions; a hard mask layer covering the first conductive plugs; and a second conductive plug between the first conductive plugs, the second conductive plug connected to the gate line by passing through the gate insulating capping layer and having a top surface higher than the top surface of each first conductive plug, wherein the hard mask layer protrudes from the first conductive plugs and toward the second conductive plug so that a portion of the hard mask layer overhangs from an edge of the first conductive plugs.

公开(公告)号：US20220223702A1

公开(公告)日：2022-07-14

申请号：US17707036

申请日：2022-03-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chang-yeon LEE ,  Jin-wook LEE ,  Min-chan GWAK ,  Kye-Hyun BAEK ,  Hong-bae PARK

IPC: H01L29/417 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/78

Abstract: An integrated circuit device including a substrate; a fin-type active region protruding from the substrate; a gate line intersecting the fin-type active region and covering a top surface and side walls thereof; a gate insulating capping layer covering the gate line; source/drain regions at sides of the gate line on the fin-type active region; first conductive plugs connected to the source/drain regions; a hard mask layer covering the first conductive plugs; and a second conductive plug between the first conductive plugs, the second conductive plug connected to the gate line by passing through the gate insulating capping layer and having a top surface higher than the top surface of each first conductive plug, wherein the hard mask layer protrudes from the first conductive plugs and toward the second conductive plug so that a portion of the hard mask layer overhangs from an edge of the first conductive plugs.

公开(公告)号：US20170032987A1

公开(公告)日：2017-02-02

申请号：US15096555

申请日：2016-04-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyung-Joo LEE ,  Kwang-Nam KIM ,  Jong-Seo HONG ,  Kye-Hyun BAEK ,  Masayuki TOMOYASU

IPC: H01L21/67 ,  H01J37/32 ,  H01L21/683

CPC classification number: H01J37/32642 ,  H01J37/32009 ,  H01J2237/334 ,  H01L21/6831 ,  H01L21/68735

Abstract: Disclosed are a dry etching apparatus and a method of etching a substrate using the same. The apparatus includes a base at a lower portion of process chamber in which a dry etching process is performed, a substrate holder arranged on the base and holding a substrate on which a plurality of pattern structures is formed by the etching process, a focus ring enclosing the substrate holder and uniformly focusing an etching plasma to a sheath area over the substrate, a driver driving the focus ring in a vertical direction perpendicular to the base and a position controller controlling a vertical position of the focus ring by selectively driving the driver in accordance with inspection results of the pattern structures. Accordingly, the gap distance between the substrate and the focus ring is automatically controlled to thereby increase the uniformity of the etching plasma over the substrate.

Abstract translation: 公开了一种干式蚀刻装置和使用其进行蚀刻的基板的方法。 该设备包括在处理室的下部处的基座，其中执行干法蚀刻工艺;衬底保持器，其布置在基底上并保持通过蚀刻工艺在其上形成多个图案结构的衬底;聚焦环封闭 衬底保持器并且均匀地将蚀刻等离子体聚焦到衬底上的护套区域上，驱动聚焦环的垂直方向与基座垂直的驱动器以及控制聚焦环的垂直位置的位置控制器通过根据 具有图案结构的检查结果。 因此，自动控制基板与聚焦环之间的间隙距离，从而增加蚀刻等离子体在基板上的均匀性。