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    DRY ETCHING APPARATUS
    2.
    发明申请
    DRY ETCHING APPARATUS 审中-公开
    干蚀设备

    公开(公告)号：US20170032987A1

    公开(公告)日：2017-02-02

    申请号：US15096555

    申请日：2016-04-12

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyung-Joo LEE ,  Kwang-Nam KIM ,  Jong-Seo HONG ,  Kye-Hyun BAEK ,  Masayuki TOMOYASU

    IPC: H01L21/67 ,  H01J37/32 ,  H01L21/683

    CPC classification number: H01J37/32642 ,  H01J37/32009 ,  H01J2237/334 ,  H01L21/6831 ,  H01L21/68735

    Abstract: Disclosed are a dry etching apparatus and a method of etching a substrate using the same. The apparatus includes a base at a lower portion of process chamber in which a dry etching process is performed, a substrate holder arranged on the base and holding a substrate on which a plurality of pattern structures is formed by the etching process, a focus ring enclosing the substrate holder and uniformly focusing an etching plasma to a sheath area over the substrate, a driver driving the focus ring in a vertical direction perpendicular to the base and a position controller controlling a vertical position of the focus ring by selectively driving the driver in accordance with inspection results of the pattern structures. Accordingly, the gap distance between the substrate and the focus ring is automatically controlled to thereby increase the uniformity of the etching plasma over the substrate.

    Abstract translation: 公开了一种干式蚀刻装置和使用其进行蚀刻的基板的方法。 该设备包括在处理室的下部处的基座，其中执行干法蚀刻工艺;衬底保持器，其布置在基底上并保持通过蚀刻工艺在其上形成多个图案结构的衬底;聚焦环封闭 衬底保持器并且均匀地将蚀刻等离子体聚焦到衬底上的护套区域上，驱动聚焦环的垂直方向与基座垂直的驱动器以及控制聚焦环的垂直位置的位置控制器通过根据 具有图案结构的检查结果。 因此，自动控制基板与聚焦环之间的间隙距离，从而增加蚀刻等离子体在基板上的均匀性。

    METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE
    4.
    发明申请
    METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE 有权
    制造半导体器件的方法

    公开(公告)号：US20170053828A1

    公开(公告)日：2017-02-23

    申请号：US15238836

    申请日：2016-08-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Chan-Hoon PARK ,  Dong-Chan KIM ,  Masayuki TOMOYASU ,  Je-Woo HAN

    IPC: H01L21/768 ,  H01L21/68 ,  H01L21/8234 ,  H01L21/66

    CPC classification number: H01L21/76897 ,  H01L21/682 ,  H01L21/76805 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823475 ,  H01L22/12 ,  H01L22/20 ,  H01L29/4983

    Abstract: A method for fabricating a semiconductor device is disclosed. The method includes forming a first interlayer insulating layer including a first trench that is defined by a first gate spacer and a second trench that is defined by a second gate spacer on a substrate, forming a first gate electrode that fills a part of the first trench and a second gate electrode that fills a part of the second trench, forming a first capping pattern that fills the remainder of the first trench on the first gate electrode, forming a second capping pattern that fills the remainder of the second trench on the second gate electrode, forming a second interlayer insulating layer that covers the first gate spacer and the second gate spacer on the first interlayer insulating layer, forming a third interlayer insulating layer on the second interlayer insulating layer and forming a contact hole that penetrates the third interlayer insulating layer and the second interlayer insulating layer between the first gate electrode and the second gate electrode.

    Abstract translation: 公开了一种制造半导体器件的方法。 该方法包括形成第一层间绝缘层，该第一层间绝缘层包括由第一栅极隔离物限定的第一沟槽和由衬底上的第二栅极间隔物限定的第二沟槽，形成第一栅电极，其填充第一沟槽的一部分 以及第二栅电极，其填充所述第二沟槽的一部分，形成填充所述第一栅电极上的所述第一沟槽的剩余部分的第一封盖图案，形成填充所述第二栅极上的所述第二沟槽的其余部分的第二封盖图案 形成覆盖所述第一层间绝缘层上的所述第一栅极间隔物和所述第二栅极间隔物的第二层间绝缘层，在所述第二层间绝缘层上形成第三层间绝缘层，形成贯通所述第三层间绝缘层的接触孔 以及第一栅电极和第二栅电极之间的第二层间绝缘层。

    CAPACITIVELY-COUPLED PLASMA SUBSTRATE PROCESSING APPARATUS INCLUDING A FOCUS RING AND A SUBSTRATE PROCESSING METHOD USING THE SAME
    6.
    发明申请
    CAPACITIVELY-COUPLED PLASMA SUBSTRATE PROCESSING APPARATUS INCLUDING A FOCUS RING AND A SUBSTRATE PROCESSING METHOD USING THE SAME 审中-公开

    公开(公告)号：US20200335376A1

    公开(公告)日：2020-10-22

    申请号：US16683707

    申请日：2019-11-14

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jongwoo SUN ,  Incheol SONG ,  Hongmin YOON ,  Jihyun LIM ,  Masayuki TOMOYASU ,  Jewoo HAN

    IPC: H01L21/683 ,  H01J37/32

    Abstract: According to some embodiments, a semiconductor substrate processing apparatus includes a housing, a plasma source unit, an electrostatic chuck, and a ring unit. The housing encloses a process chamber. The plasma source unit is connected to the housing, and includes a shower head and a fixing ring positioned to support the shower head. The shower head includes an upper electrode mounted on the fixing ring, and includes injection holes passing through part of the upper electrode and configured to inject gas into the chamber. The electrostatic chuck is connected to the housing and includes a lower electrode, and is for mounting a semiconductor substrate thereon. The ring unit is mounted on an edge portion of the electrostatic chuck, and includes a focus ring and a cover ring surrounding the focus ring. One of the lower electrode and the upper electrode is connected to a high frequency power supply, and the other of the lower electrode and the upper electrode is connected to ground. The focus ring has an inner side surface, and an opposite outer side surface that contacts the cover ring, and a width between the inner side surface and the outer side surface of the focus ring is a first width. The cover ring has an inner side surface that contacts the outer side surface of the focus ring, and an outer side surface, and a width between the inner side surface and the outer side surface of the cover ring is a second width. The first width is between 2 and 10 time the second width.

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