EAR WEARABLE DEVICE
    2.
    发明申请

    公开(公告)号:US20210250676A1

    公开(公告)日:2021-08-12

    申请号:US17173030

    申请日:2021-02-10

    IPC分类号: H04R1/10

    摘要: An ear wearable device includes a housing, a speaker, a structure, nonconductive supporting member, and an Integrated Circuit (IC). The housing includes a nonconductive cover. The speaker is positioned in the housing. The structure is positioned in the housing and includes a nonconductive supporting member facing the nonconductive cover and positioned in the housing, and a first conductive pattern positioned on the nonconductive supporting member. The nonconductive bonding member is positioned between the structure and the nonconductive cover. The touch sensor IC is positioned in the housing and electrically connected with the first conductive pattern.

    ELECTRONIC DEVICE INCLUDING MICROPHONE MODULE

    公开(公告)号:US20230188878A1

    公开(公告)日:2023-06-15

    申请号:US17994195

    申请日:2022-11-25

    IPC分类号: H04R1/04 H04M1/02

    摘要: An electronic device is provided. The electronic device includes a housing, a support member disposed inside the housing and forming a connection passage, a printed circuit board disposed on the support member and including a first area and a second area spaced apart from the first area, and a conductive pattern disposed on the support member and including a first portion and a second portion, wherein the first portion may be electrically connected to a first electrode disposed in the first area, the second portion may be electrically connected to a second electrode disposed in the second area, and the first area and the second area may be electrically connected to each other via a shunt member.

    DEVICE AND METHOD WITH DATA PREPROCESSING

    公开(公告)号:US20220398685A1

    公开(公告)日:2022-12-15

    申请号:US17558686

    申请日:2021-12-22

    IPC分类号: G06T1/20 G06N20/00

    摘要: A device and method with data preprocessing are disclosed. The device with preprocessing includes a first memory configured to store raw data, and a field programmable gate array (FPGA) in which reconfigurable augmentation modules are programmed, where the FPGA includes a decoder configured to decode the raw data, a second memory configured to store the decoded raw data, and a processor, where the processor is configured to determine target augmentation modules, from among the reconfigurable augmentation modules, based on a data preprocessing pipeline, perform the data preprocessing pipeline using the determined target augmentation modules to generate augmented data, including an augmentation of at least a portion of the decoded raw data stored in the second memory using an idle augmentation module, from among the target augmentation modules, and implement provision of the augmented data to a graphics processing unit (GPU) or Neural Processing Unit (NPU).