公开(公告)号：US12261105B2

公开(公告)日：2025-03-25

申请号：US18098158

申请日：2023-01-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myungsam Kang ,  Youngchan Ko ,  Jeongseok Kim ,  Kyung Don Mun ,  Bongju Cho

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538

Abstract: A semiconductor package includes a redistribution substrate having a dielectric layer and a wiring pattern in the dielectric layer, the wiring pattern including a line part that extends horizontally, and a via part connected to the line part, the via part having a width less than a width of the line part, a passivation layer on a top surface of the redistribution substrate, the passivation layer including a material different from a material of the dielectric layer, a conductive pillar that penetrates the passivation layer, the conductive pillar being connected to the via part, and a connection terminal on a top surface of the conductive pillar, a distance between the top surface of the conductive pillar and a top surface of the passivation layer being greater than a thickness of the passivation layer.

公开(公告)号：US20240332270A1

公开(公告)日：2024-10-03

申请号：US18475863

申请日：2023-09-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangjin Baek ,  Kyung Don Mun ,  Ji Hwang Kim ,  Kyoung Lim Suk

IPC: H01L25/16 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L25/16 ,  H01L21/56 ,  H01L23/3128 ,  H01L24/06 ,  H01L24/08 ,  H01L24/16 ,  H01L24/80 ,  H01L24/81 ,  H01L28/40 ,  H01L2224/06181 ,  H01L2224/08145 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/81801

Abstract: The present disclosure relates to semiconductor packages and methods for manufacturing semiconductor packages. An example semiconductor package includes a top die, first and second bottom dies attached on a lower surface of the top die and being apart from each other by a preset distance, and at least one decoupling capacitor connected to the lower surface of the top die between the first bottom die and the second bottom die. The top die, the first bottom die, and the second bottom die are chiplets.

公开(公告)号：US20240120318A1

公开(公告)日：2024-04-11

申请号：US18312331

申请日：2023-05-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung Don Mun ,  Sang Cheon Park

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/522 ,  H10B80/00

CPC classification number: H01L25/0657 ,  H01L23/3107 ,  H01L23/5226 ,  H01L24/08 ,  H10B80/00 ,  H01L2224/08145

Abstract: A semiconductor package includes a buffer die, semiconductor chip stacks stacked on the buffer die, each of the semiconductor chip stacks including a plurality of first semiconductor chips and a second semiconductor chip on the plurality of first semiconductor chips, and a mold layer covering an upper surface of the buffer die and side surfaces of the semiconductor chip stacks. Each of the first semiconductor chips and the second semiconductor chip includes a wiring part including multilayer wirings, an upper connection structure on the wiring part and having a plurality of upper conductive pads and a lower connection structure under the wiring part and having a plurality of lower conductive pads, and the second semiconductor chip further includes a redistribution layer on the upper connection structure and having an insulating layer and a plurality of redistribution pads in the insulating layer.

公开(公告)号：US11916002B2

公开(公告)日：2024-02-27

申请号：US17551938

申请日：2021-12-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myungsam Kang ,  Youngchan Ko ,  Jeongseok Kim ,  Kyung Don Mun

IPC: H01L23/498 ,  H01L23/31 ,  H01L25/18 ,  H01L23/00 ,  H01L23/538

CPC classification number: H01L23/49822 ,  H01L23/3157 ,  H01L23/49811 ,  H01L23/5389 ,  H01L24/08 ,  H01L25/18 ,  H01L2224/08235

Abstract: Disclosed is a semiconductor package comprising a package substrate, an interposer substrate on the package substrate and including a first redistribution substrate, a second redistribution substrate on a bottom surface of the first redistribution substrate, and an interposer molding layer between the first redistribution substrate and the second redistribution substrate, a connection substrate on the interposer substrate and having a connection hole that penetrates the connection substrate, a first semiconductor chip on the interposer substrate and in the connection hole, a second semiconductor chip on the interposer substrate, in the connection hole and horizontally spaced apart from the first semiconductor chip, and a connection semiconductor chip in the interposer molding layer and on the bottom surface of the first redistribution substrate.

公开(公告)号：US12183665B2

公开(公告)日：2024-12-31

申请号：US18423229

申请日：2024-01-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myungsam Kang ,  Youngchan Ko ,  Jeongseok Kim ,  Kyung Don Mun

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L25/18

Abstract: Disclosed is a semiconductor package comprising a package substrate, an interposer substrate on the package substrate and including a first redistribution substrate, a second redistribution substrate on a bottom surface of the first redistribution substrate, and an interposer molding layer between the first redistribution substrate and the second redistribution substrate, a connection substrate on the interposer substrate and having a connection hole that penetrates the connection substrate, a first semiconductor chip on the interposer substrate and in the connection hole, a second semiconductor chip on the interposer substrate, in the connection hole and horizontally spaced apart from the first semiconductor chip, and a connection semiconductor chip in the interposer molding layer and on the bottom surface of the first redistribution substrate.

公开(公告)号：US12062632B2

公开(公告)日：2024-08-13

申请号：US18141838

申请日：2023-05-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyung Don Mun ,  Myungsam Kang

IPC: H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/538 ,  H01L25/00 ,  H01L25/10

CPC classification number: H01L24/20 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/19 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2224/214 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058

Abstract: Provided is a semiconductor package device including a lower redistribution substrate including a first redistribution pattern, the first redistribution pattern including a first interconnection portion and a first via portion provided on the first interconnection portion, a semiconductor chip disposed on the lower redistribution substrate, the semiconductor chip including a chip pad facing the lower redistribution substrate, an upper redistribution substrate vertically spaced apart from the lower redistribution substrate, the upper redistribution substrate including a second redistribution pattern, a vertical conductive structure disposed between the lower redistribution substrate and the upper redistribution substrate and disposed at a side of the semiconductor chip, a third redistribution pattern disposed between the lower redistribution substrate and the vertical conductive structure, and an encapsulant disposed on the semiconductor chip, the vertical conductive structure, and the third redistribution pattern, wherein the first via portion is in contact with the third redistribution pattern, and wherein a level of a bottom surface of the vertical conductive structure is higher than a level of a bottom surface of the chip pad.

公开(公告)号：US11676927B2

公开(公告)日：2023-06-13

申请号：US17317309

申请日：2021-05-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyung Don Mun ,  Myungsam Kang

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00 ,  H01L25/10

CPC classification number: H01L24/20 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/19 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2224/214 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058

Abstract: Provided is a semiconductor package device including a lower redistribution substrate including a first redistribution pattern, the first redistribution pattern including a first interconnection portion and a first via portion provided on the first interconnection portion, a semiconductor chip disposed on the lower redistribution substrate, the semiconductor chip including a chip pad facing the lower redistribution substrate, an upper redistribution substrate vertically spaced apart from the lower redistribution substrate, the upper redistribution substrate including a second redistribution pattern, a vertical conductive structure disposed between the lower redistribution substrate and the upper redistribution substrate and disposed at a side of the semiconductor chip, a third redistribution pattern disposed between the lower redistribution substrate and the vertical conductive structure, and an encapsulant disposed on the semiconductor chip, the vertical conductive structure, and the third redistribution pattern, wherein the first via portion is in contact with the third redistribution pattern, and wherein a level of a bottom surface of the vertical conductive structure is higher than a level of a bottom surface of the chip pad.

公开(公告)号：US11569158B2

公开(公告)日：2023-01-31

申请号：US17228784

申请日：2021-04-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myungsam Kang ,  Youngchan Ko ,  Jeongseok Kim ,  Kyung Don Mun ,  Bongju Cho

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L23/31

Abstract: A semiconductor package includes a redistribution substrate having a dielectric layer and a wiring pattern in the dielectric layer, the wiring pattern including a line part that extends horizontally, and a via part connected to the line part, the via part having a width less than a width of the line part, a passivation layer on a top surface of the redistribution substrate, the passivation layer including a material different from a material of the dielectric layer, a conductive pillar that penetrates the passivation layer, the conductive pillar being connected to the via part, and a connection terminal on a top surface of the conductive pillar, a distance between the top surface of the conductive pillar and a top surface of the passivation layer being greater than a thickness of the passivation layer.