公开(公告)号：US20240347468A1

公开(公告)日：2024-10-17

申请号：US18754434

申请日：2024-06-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myungsam Kang ,  Youngchan Ko ,  Jeongseok Kim ,  Bongju Cho

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/31 ,  H01L25/10

CPC classification number: H01L23/5389 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/19 ,  H01L24/20 ,  H01L25/105 ,  H01L2221/68372 ,  H01L2224/214 ,  H01L2224/215 ,  H01L2225/1035 ,  H01L2225/1058

Abstract: A semiconductor package includes a first redistribution structure having a first surface in which a first pad and a second pad are embedded and including a first redistribution layer thereon, and a vertical connection structure including a land layer and a pillar layer. The land layer is embedded in the first surface of the first redistribution structure, and a width of an upper surface of the land layer is narrower than a width of a lower surface of the pillar layer.

公开(公告)号：US20240321755A1

公开(公告)日：2024-09-26

申请号：US18391844

申请日：2023-12-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myungsam Kang

IPC: H01L23/538 ,  H01L23/15 ,  H01L25/065 ,  H10B80/00

CPC classification number: H01L23/5384 ,  H01L23/15 ,  H01L23/5381 ,  H01L23/5383 ,  H01L25/0652 ,  H01L25/0657 ,  H10B80/00 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/0651 ,  H01L2225/06562

Abstract: Provided is a semiconductor package capable of minimizing the size of a silicon (Si) interposer and minimizing warpage of a package substrate while maintaining a chip-to-chip connection function. The semiconductor package includes a package substrate including a glass core substrate, a silicon (Si) bridge interposer, and a multi-layer wiring layer disposed under the glass core substrate and the Si bridge interposer, and at least two semiconductor devices stacked on the package substrate, wherein a cavity is formed in a central portion of the glass core substrate, and the Si bridge interposer is embedded in the cavity.

公开(公告)号：US11784129B2

公开(公告)日：2023-10-10

申请号：US17183562

申请日：2021-02-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myungsam Kang ,  Youngchan Ko ,  Taesung Jeong

IPC: H01L23/538 ,  H01L23/498 ,  H01L23/00 ,  H01L21/48 ,  H01L23/31

CPC classification number: H01L23/5383 ,  H01L21/486 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/3107 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5386 ,  H01L24/20 ,  H01L2224/211 ,  H01L2224/214

Abstract: A semiconductor package and associated methods, the package including a substrate; first and second semiconductor chips on the substrate; and external terminals below the substrate, wherein the substrate includes a core portion; first and second buildup portions on top and bottom surfaces of the core portion, the first and second buildup portions including a dielectric pattern and a line pattern; and an interposer chip in an embedding region in the core portion and electrically connected to the first and second buildup portions, the interposer chip includes a base layer; a redistribution layer on the base layer; and a via that penetrates the base layer, the via being connected to the redistribution layer and exposed at a surface of the base layer, the redistribution layer is connected to a line pattern of the first buildup portion, and the via is connected to a line pattern of the second buildup portion.

公开(公告)号：US20230178492A1

公开(公告)日：2023-06-08

申请号：US18161066

申请日：2023-01-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungdon Mun ,  Myungsam Kang ,  Youngchan Ko ,  Yieok Kwon ,  Jeongseok Kim ,  Gongje Lee ,  Bongju Cho

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/498 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/5386 ,  H01L25/0657 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/73 ,  H01L23/3128 ,  H01L24/08 ,  H01L23/5385 ,  H01L2224/08235 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2224/73204

Abstract: A semiconductor package includes a redistribution substrate including a first redistribution layer; a semiconductor chip electrically connected to the first redistribution layer; a vertical connection structure adjacent a periphery of the semiconductor chip and electrically connected to the first redistribution layer; and an encapsulant on the vertical connection structure. The vertical connection structure includes a metal pillar having a bottom surface facing the redistribution substrate, a top surface positioned opposite to the bottom surface, and a side surface positioned between the bottom surface and the top surface. The vertical connection structure further includes a plating layer on each of the bottom surface, the top surface, and the side surface of the metal pillar, and having a roughened surface.

公开(公告)号：US11569175B2

公开(公告)日：2023-01-31

申请号：US17239141

申请日：2021-04-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungdon Mun ,  Myungsam Kang ,  Youngchan Ko ,  Yieok Kwon ,  Jeongseok Kim ,  Gongje Lee ,  Bongju Cho

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/498 ,  H01L23/00 ,  H01L23/31

Abstract: A semiconductor package includes a redistribution substrate including a first redistribution layer; a semiconductor chip electrically connected to the first redistribution layer; a vertical connection structure adjacent a periphery of the semiconductor chip and electrically connected to the first redistribution layer; and an encapsulant on the vertical connection structure. The vertical connection structure includes a metal pillar having a bottom surface facing the redistribution substrate, a top surface positioned opposite to the bottom surface, and a side surface positioned between the bottom surface and the top surface. The vertical connection structure further includes a plating layer on each of the bottom surface, the top surface, and the side surface of the metal pillar, and having a roughened surface.

公开(公告)号：US20220068822A1

公开(公告)日：2022-03-03

申请号：US17239141

申请日：2021-04-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungdon Mun ,  Myungsam Kang ,  Youngchan Ko ,  Yieok Kwon ,  Jeongseok Kim ,  Gongje Lee ,  Bongju Cho

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/498 ,  H01L23/00 ,  H01L23/31

Abstract: A semiconductor package includes a redistribution substrate including a first redistribution layer; a semiconductor chip electrically connected to the first redistribution layer; a vertical connection structure adjacent a periphery of the semiconductor chip and electrically connected to the first redistribution layer; and an encapsulant on the vertical connection structure. The vertical connection structure includes a metal pillar having a bottom surface facing the redistribution substrate, a top surface positioned opposite to the bottom surface, and a side surface positioned between the bottom surface and the top surface. The vertical connection structure further includes a plating layer on each of the bottom surface, the top surface, and the side surface of the metal pillar, and having a roughened surface.

公开(公告)号：US12159826B2

公开(公告)日：2024-12-03

申请号：US17476670

申请日：2021-09-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myungsam Kang ,  Youngchan Ko ,  Jeongseok Kim ,  Kyungdon Mun

IPC: H01L23/522 ,  H01L21/48 ,  H01L23/00 ,  H01L23/498

Abstract: A semiconductor package includes a support substrate having connection wirings disposed therein. At least one capacitor is disposed on the support substrate. The capacitor has first and second electrodes that are exposed from an upper surface of the support substrate. A redistribution wiring layer covers the upper surface of the support substrate. The redistribution wiring layer has redistribution wirings electrically connected to the connection wirings and the first and second electrodes respectively. A semiconductor chip is disposed on the redistribution wiring layer. The semiconductor chip has chip pads that are electrically connected to the redistribution wirings and outer connectors disposed on a lower surface of the support substrate and electrically connected to the connection wirings.

公开(公告)号：US12094817B2

公开(公告)日：2024-09-17

申请号：US18125529

申请日：2023-03-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myungsam Kang ,  Youngchan Ko ,  Kyungdon Mun

IPC: H01L23/522 ,  H01L23/00 ,  H01L23/31 ,  H01L23/36

CPC classification number: H01L23/5226 ,  H01L23/31 ,  H01L23/36 ,  H01L24/14 ,  H01L24/19 ,  H01L24/20

Abstract: A semiconductor package includes a redistribution substrate including a first redistribution layer; a semiconductor chip having a connection pad connected to the first redistribution layer; a vertical connection conductor electrically connected to the connection pad by the first redistribution layer; a core member having a first through-hole accommodating the semiconductor chip and a second through-hole accommodating the vertical connection conductor; an encapsulant filling the first and second through-holes; and a redistribution member including a second redistribution layer. The vertical connection conductor and the core member include a same material. A width of a lower surface of the vertical connection conductor is wider than that of an upper surface thereof, a width of a lower end of the first through-hole is narrower than that of an upper end thereof, and a width of a lower end of the second through-hole is narrower than that of an upper end thereof.

公开(公告)号：US12040297B2

公开(公告)日：2024-07-16

申请号：US18166869

申请日：2023-02-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myungsam Kang ,  Youngchan Ko ,  Jeongseok Kim ,  Kyungdon Mun

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/522

CPC classification number: H01L24/14 ,  H01L23/49811 ,  H01L23/5226 ,  H01L24/05

Abstract: A semiconductor package includes a redistribution structure including an insulating layer and a redistribution layer on the insulating layer, and having a first surface and a second surface opposing the first surface, and an under-bump metal (UBM) structure including an UBM pad protruding from the first surface of the redistribution structure, and an UBM via penetrating through the insulating layer and connecting the redistribution layer and the UBM pad. A lower surface of the UBM via has a first area in contact with the UBM pad, and a second area having a step configuration relative to the first area and that extends outwardly of the first area.

公开(公告)号：US11935849B2

公开(公告)日：2024-03-19

申请号：US18061763

申请日：2022-12-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myungsam Kang ,  Sangkyu Lee ,  Yongkoon Lee

IPC: H01L23/66 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L23/552 ,  H01Q1/22 ,  H01Q1/52 ,  H01Q21/06

CPC classification number: H01L23/66 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/19 ,  H01L24/20 ,  H01Q1/2283 ,  H01Q1/523 ,  H01Q1/526 ,  H01L2223/6677 ,  H01L2224/214 ,  H01L2924/19106 ,  H01L2924/3025 ,  H01Q21/065

Abstract: A semiconductor package includes a front redistribution structure having a first surface and a second surface, opposite to the first surface, a dielectric layer, an antenna substrate including a plurality of antenna members in the dielectric layer, a semiconductor chip having a connection pad connected to the plurality of antenna members, a conductive core structure having a first through-hole accommodating the antenna substrate and a second through-hole accommodating the semiconductor chip, and a rear redistribution structure including a conductive cover layer exposing an upper portion of the antenna substrate and covering an upper portion of the semiconductor chip, and a conductive via connecting the conductive cover layer to the conductive core structure.