公开(公告)号：US20230402076A1

公开(公告)日：2023-12-14

申请号：US18455904

申请日：2023-08-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byunghoon JEONG ,  Kyungtae KANG ,  Jangwoo LEE ,  Jeongdon IHM

IPC: G11C7/22 ,  G11C7/10 ,  H03K19/173 ,  G11C8/18 ,  G11C29/42

CPC classification number: G11C7/222 ,  G11C7/1057 ,  G11C7/1063 ,  H03K19/1737 ,  G11C8/18 ,  G11C29/42 ,  G11C7/1084

Abstract: A memory device includes a memory cell array configured to store data; and a data output circuit configured to transmit status data to an external device through at least one data line in a latency period in response to a read enable signal received from the external device and transmit the data read from the memory cell array to the external device through the at least one data line in a period subsequent to the latency period.

公开(公告)号：US20210383848A1

公开(公告)日：2021-12-09

申请号：US17411421

申请日：2021-08-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byunghoon JEONG ,  Kyungtae KANG ,  Jangwoo LEE ,  Jeongdon IHM

IPC: G11C7/22 ,  G11C7/10 ,  G11C8/18 ,  G11C29/42 ,  H03K19/173

Abstract: A memory device includes a memory cell array configured to store data; and a data output circuit configured to transmit status data to an external device through at least one data line in a latency period in response to a read enable signal received from the external device and transmit the data read from the memory cell array to the external device through the at least one data line in a period subsequent to the latency period.

公开(公告)号：US20210226613A1

公开(公告)日：2021-07-22

申请号：US17222033

申请日：2021-04-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongho SHIN ,  Kyungtae KANG ,  Junha LEE ,  Tongsung KIM ,  Jangwoo LEE ,  Jeongdon IHM ,  Byunghoon JEONG

IPC: H03K3/017 ,  H03K19/21 ,  H03K5/24

Abstract: A method of operating a system including a parameter monitoring circuit and a host, includes generating a first parameter applying a first code to a current parameter, wherein a first offset is applied to the first code; generating a first comparison result by comparing the first parameter with a reference parameter value; generating a second parameter applying a second code to the current parameter, wherein a second offset is applied to the second code; generating a second comparison result by comparing the second parameter with the reference parameter value; detecting an error in the current parameter, based on the first comparison result and the second comparison result; and providing a signal based on the error to the host.

公开(公告)号：US20210075405A1

公开(公告)日：2021-03-11

申请号：US16861903

申请日：2020-04-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongho SHIN ,  Kyungtae KANG ,  Junha LEE ,  Tongsung KIM ,  Jangwoo LEE ,  Jeongdon IHM ,  Byunghoon JEONG

IPC: H03K3/017 ,  H03K5/24 ,  H03K19/21

Abstract: A parameter monitoring circuit includes a code generation circuit configured to generate a first code, to which a first offset is applied, and a second code, to which a second offset is applied; a parameter adjustment circuit configured to generate a first parameter and a second parameter by respectively applying the first code and the second code to a current parameter; a comparator circuit configured to generate a first comparison result and a second comparison result, the first comparison result indicating a comparison result between the first parameter and a reference parameter value, and the second comparison result indicating a comparison result between the second parameter and the reference parameter value; and a parameter error detection circuit configured to detect an error in the current parameter, based on the first comparison result and the second comparison result.

公开(公告)号：US20230127635A1

公开(公告)日：2023-04-27

申请号：US18069685

申请日：2022-12-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byunghoon JEONG ,  Kyungtae KANG ,  Jangwoo LEE

IPC: G11C7/22 ,  G11C7/10 ,  H03K19/173 ,  G11C8/18 ,  G11C29/42

Abstract: A memory device includes a memory cell array configured to store data; and a data output circuit configured to transmit status data to an external device through at least one data line in a latency period in response to a read enable signal received from the external device and transmit the data read from the memory cell array to the external device through the at least one data line in a period subsequent to the latency period.

公开(公告)号：US20210104267A1

公开(公告)日：2021-04-08

申请号：US17001941

申请日：2020-08-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byunghoon JEONG ,  Kyungtae KANG ,  Jangwoo LEE ,  Jeongdon IHM

IPC: G11C7/22 ,  G11C7/10 ,  G11C7/04

Abstract: A memory device includes a memory cell array configured to store data; and a data output circuit configured to transmit status data to an external device through at least one data line in a latency period in response to a read enable signal received from the external device and transmit the data read from the memory cell array to the external device through the at least one data line in a period subsequent to the latency period.