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    Clock gating circuit
    1.
    发明授权
    Clock gating circuit 有权

    公开(公告)号：US10566977B2

    公开(公告)日：2020-02-18

    申请号：US16259631

    申请日：2019-01-28

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Ah-Reum Kim ,  Hyun Lee ,  Min-su Kim

    IPC: H03K3/356 ,  H03K19/0185 ,  H03K19/00 ,  H03K3/037 ,  H03K3/012

    Abstract: Provided are semiconductor circuits. A semiconductor circuit includes: a first circuit configured to propagate a value of a first node to a second node based on a voltage level of a clock signal; a second circuit configured to propagate a value of the second node to a third node based on the voltage level of the clock signal; and a third circuit configured to determine a value of the third node based on a voltage level of the second node and the voltage level of the clock signal, wherein the first circuit comprises a first transistor gated to a voltage level of the first node, a second transistor connected in series with the first transistor and gated to the voltage level of the third node, and a third transistor connected in parallel with the first and second transistors and gated to a voltage level of the clock signal to provide the value of the first node to the second node.

    INTEGRATED CIRCUIT INCLUDING STANDARD CELL AND METHOD AND SYSTEM FOR DESIGNING AND MANUFACTURING THE SAME
    2.
    发明申请
    INTEGRATED CIRCUIT INCLUDING STANDARD CELL AND METHOD AND SYSTEM FOR DESIGNING AND MANUFACTURING THE SAME 审中-公开

    公开(公告)号：US20190325107A1

    公开(公告)日：2019-10-24

    申请号：US16387837

    申请日：2019-04-18

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： KYUNG-BONG KIM ,  Min-su Kim ,  Dae-seong Lee

    IPC: G06F17/50 ,  H01L23/522 ,  H01L27/02

    Abstract: An integrated circuit including standard cells, a method and a computing system for designing and fabricating the same are provided. A computer-implemented method involves placing, based on a standard cell library, standard cells of an integrated circuit to be fabricated, and routing the placed standard cells. A position of a first wiring of a placed cell among the placed standard cells may be adjusted based on a position of a second wiring used for the routing. The first wiring is provided from at least one standard cell, formed in a same layer as that of the second wiring, and spaced from the second wiring in a first direction. An integrated circuit layout having the adjusted position of the first wiring, is produced.

    Clock gating circuit
    3.
    再颁专利
    Clock gating circuit 有权

    公开(公告)号：USRE50010E1

    公开(公告)日：2024-06-11

    申请号：US17672371

    申请日：2022-02-15

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Ah-Reum Kim ,  Hyun Lee ,  Min-su Kim

    IPC: H03K3/356 ,  H03K3/012 ,  H03K3/037 ,  H03K19/00 ,  H03K19/0185

    CPC classification number: H03K19/01855 ,  H03K3/012 ,  H03K3/037 ,  H03K3/356104 ,  H03K3/356191 ,  H03K19/0013

    Abstract: Provided are semiconductor circuits. A semiconductor circuit includes a first circuit configured to propagate a value of a first node to a second node based on a voltage level of a clock signal; a second circuit configured to propagate a value of the second node to a third node based on the voltage level of the clock signal; and a third circuit configured to determine a value of the third node based on a voltage level of the second node and the voltage level of the clock signal, wherein the first circuit comprises a first transistor gated to a voltage level of the first node, a second transistor connected in series with the first transistor and gated to the voltage level of the third node, and a third transistor connected in parallel with the first and second transistors and gated to a voltage level of the clock signal to provide the value of the first node to the second node.

    Integrated circuits and methods of manufacturing and designing the same
    5.
    发明授权
    Integrated circuits and methods of manufacturing and designing the same 有权

    公开(公告)号：US11031384B2

    公开(公告)日：2021-06-08

    申请号：US16506389

    申请日：2019-07-09

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Min-su Kim

    IPC: H01L27/02 ,  H01L23/00 ,  H01L23/528 ,  G06F30/39 ,  H01L27/06 ,  H01L27/118

    Abstract: Provided is an integrated circuit including a semiconductor substrate, a plurality of gate lines and a plurality of metal lines. The plurality of gate lines are formed in a gate layer above the semiconductor substrate, where the plurality of gate lines are arranged in a first direction and extend in a second direction perpendicular to the second direction. The plurality of metal lines are formed in a conduction layer above the gate layer, where the plurality of metal lines are arranged in the first direction and extend in the second direction. 6N metal lines and 4N gate lines form a unit wiring structure where N is a positive integer and a plurality of unit wiring structures are arranged in the first direction. Design efficiency and performance of the integrated circuit are enhanced through the unit wiring structure.

    LED driving apparatus, lighting apparatus including the same, and method of driving LED module
    6.
    发明授权
    LED driving apparatus, lighting apparatus including the same, and method of driving LED module 有权

    公开(公告)号：US10104741B2

    公开(公告)日：2018-10-16

    申请号：US15670331

    申请日：2017-08-07

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seung-kwan Choi ,  Min-su Kim

    IPC: H05B37/02 ,  H05B33/08

    Abstract: A light-emitting diode (LED) driving apparatus driving an LED module includes: a first output circuit configured to supply a first driving current to a first LED array; a second output circuit configured to supply a second driving current to a second LED array; and a controller configured to transmit a first control signal and a second control signal respectively to the first output circuit and the second output circuit, wherein the controller is further configured to control the LED module based on the first input signal so that a color temperature of the LED module has a value between a first color temperature and a second color temperature, to control brightness of the LED module based on the second input signal, and includes a lookup table including information about the first control signal and the second control signal respectively corresponding to the first input signal and the second input signal.

    LED DRIVING APPARATUS, LIGHTING APPARATUS INCLUDING THE SAME, AND METHOD OF DRIVING LED MODULE
    7.
    发明申请
    LED DRIVING APPARATUS, LIGHTING APPARATUS INCLUDING THE SAME, AND METHOD OF DRIVING LED MODULE 审中-公开

    公开(公告)号：US20180242422A1

    公开(公告)日：2018-08-23

    申请号：US15670331

    申请日：2017-08-07

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seung-kwan Choi ,  Min-su Kim

    IPC: H05B33/08

    CPC classification number: H05B33/0857 ,  H05B33/0818 ,  H05B33/0842 ,  H05B33/0845

    Abstract: A light-emitting diode (LED) driving apparatus driving an LED module includes: a first output circuit configured to supply a first driving current to a first LED array; a second output circuit configured to supply a second driving current to a second LED array; and a controller configured to transmit a first control signal and a second control signal respectively to the first output circuit and the second output circuit, wherein the controller is further configured to control the LED module based on the first input signal so that a color temperature of the LED module has a value between a first color temperature and a second color temperature, to control brightness of the LED module based on the second input signal, and includes a lookup table including information about the first control signal and the second control signal respectively corresponding to the first input signal and the second input signal.

    Memory device including plurality of latches and system on chip including the same
    9.
    发明授权
    Memory device including plurality of latches and system on chip including the same 有权

    公开(公告)号：US11289138B2

    公开(公告)日：2022-03-29

    申请号：US17104592

    申请日：2020-11-25

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Young-shin Yoo ,  Min-su Kim ,  Hyun-chul Hwang

    IPC: G11C7/10 ,  G11C7/22 ,  G06F3/06 ,  G11C8/10

    Abstract: A memory device includes a plurality of latches arranged in a plurality of columns including a first column and a second column and in a plurality of rows, a first flip flop configured to output first data, to first latches arranged in the first column, among the plurality of latches, based on a clock, and a second flip flop configured to output second data, to second latches arranged in the second column, among the plurality of latches, based on the clock. The first flip flop is further configured to, in a lock time section in which the first latches and the second latches maintain an output regardless of an input, block output of the first data to the first latches, and the second flip flop is further configured to, in the lock time section, block output of the second data to the second latches.

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