公开(公告)号：US08922024B2

公开(公告)日：2014-12-30

申请号：US13829939

申请日：2013-03-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minok Na ,  Okgyeong Park ,  Ji-Hyun Park

IPC: H01L23/522 ,  H01L23/36 ,  H01L23/498 ,  H01L21/56 ,  H01L25/10 ,  H01L23/31

CPC classification number: H01L23/5226 ,  H01L21/563 ,  H01L21/566 ,  H01L23/3185 ,  H01L23/36 ,  H01L23/49816 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Semiconductor packages including molding layer and methods of fabricating the same are provided. The method may include forming a bare package including a semiconductor chip on a package substrate and forming a molding layer surrounding the semiconductor chip on the package substrate while contacting an upper surface of the molding layer with a lower surface of a release film. The lower surface of the release film and the upper surface of the molding layer comprising uneven surfaces and the molding layer may expose an upper surface of the semiconductor chip.

Abstract translation: 提供了包括成型层的半导体封装及其制造方法。 该方法可以包括在封装衬底上形成包括半导体芯片的裸露封装，并且在模制层的上表面与脱模膜的下表面接触的同时，形成围绕封装衬底上的半导体芯片的模塑层。 脱模膜的下表面和包含不均匀表面的成型层的上表面和成型层可暴露半导体芯片的上表面。