公开(公告)号：US10056375B2

公开(公告)日：2018-08-21

申请号：US15687929

申请日：2017-08-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Doo-Young Lee ,  Sang-Hyun Lee ,  Myung-Hoon Jung ,  Do-Hyoung Kim

IPC: H01L21/00 ,  H01L27/088 ,  H01L21/768 ,  H01L21/28 ,  H01L29/45 ,  H01L29/417 ,  H01L27/02 ,  H01L21/8234 ,  H01L29/78 ,  H01L27/11

CPC classification number: H01L27/088 ,  H01L21/28114 ,  H01L21/76804 ,  H01L21/76805 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76897 ,  H01L21/823425 ,  H01L21/823475 ,  H01L23/485 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/1104 ,  H01L29/41758 ,  H01L29/41775 ,  H01L29/45 ,  H01L29/78

Abstract: A semiconductor device includes a first gate pattern and a second gate pattern on a substrate, the first gate pattern having a first height and the second gate pattern having a second height, an insulating pattern on the substrate covering the first and second gate patterns, the insulating pattern including a trench exposing the substrate between the first and second gate patterns, a spacer contacting at least a portion of a sidewall of the insulating pattern within the trench, the spacer spaced apart from the first and second gate patterns and having a third height larger than the first and second heights, and a contact structure filling the trench.

公开(公告)号：US08946069B2

公开(公告)日：2015-02-03

申请号：US14138721

申请日：2013-12-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-Wook Lee ,  Myeong-Cheol Kim ,  Sang-Min Lee ,  Young-Ju Park ,  Hyung-Yong Kim ,  Myung-Hoon Jung

IPC: H01L21/336 ,  H01L29/66 ,  H01L21/265 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/78

CPC classification number: H01L29/7848 ,  H01L21/26506 ,  H01L21/30608 ,  H01L21/3065 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/11 ,  H01L29/66636 ,  H01L29/78

Abstract: A fabricating method of a semiconductor device includes providing a substrate having a first region and a second region, forming a plurality of first gates in the first region of the substrate, such that the first gates are spaced apart from each other at a first pitch, forming a plurality of second gates in the second region of the substrate, such that the second gates are spaced apart from each other at a second pitch different from the first pitch, implanting an etch rate adjusting dopant into the second region to form implanted regions, while blocking the first region, forming a first trench by etching the first region between the plurality of first gates, and forming a second trench by etching the second region between the plurality of second gates.

Abstract translation: 半导体器件的制造方法包括提供具有第一区域和第二区域的衬底，在衬底的第一区域中形成多个第一栅极，使得第一栅极以第一间距相互间隔开， 在所述衬底的所述第二区域中形成多个第二栅极，使得所述第二栅极以不同于所述第一间距的第二间距彼此间隔开，将蚀刻速率调节掺杂剂注入所述第二区域以形成注入区域， 同时阻挡第一区域，通过蚀刻多个第一栅极之间的第一区域形成第一沟槽，并且通过蚀刻多个第二栅极之间的第二区域形成第二沟槽。

公开(公告)号：US09484458B2

公开(公告)日：2016-11-01

申请号：US14602716

申请日：2015-01-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jin-Wook Lee ,  Myeong-Cheol Kim ,  Sang-Min Lee ,  Young-Ju Park ,  Hyung-Yong Kim ,  Myung-Hoon Jung

IPC: H01L29/78 ,  H01L21/265 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/66 ,  H01L27/11

CPC classification number: H01L29/7848 ,  H01L21/26506 ,  H01L21/30608 ,  H01L21/3065 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/11 ,  H01L29/66636 ,  H01L29/78

Abstract: A fabricating method of a semiconductor device includes providing a substrate having a first region and a second region, forming a plurality of first gates in the first region of the substrate, such that the first gates are spaced apart from each other at a first pitch, forming a plurality of second gates in the second region of the substrate, such that the second gates are spaced apart from each other at a second pitch different from the first pitch, implanting an etch rate adjusting dopant into the second region to form implanted regions, while blocking the first region, forming a first trench by etching the first region between the plurality of first gates, and forming a second trench by etching the second region between the plurality of second gates.

Abstract translation: 半导体器件的制造方法包括提供具有第一区域和第二区域的衬底，在衬底的第一区域中形成多个第一栅极，使得第一栅极以第一间距相互间隔开， 在所述衬底的所述第二区域中形成多个第二栅极，使得所述第二栅极以不同于所述第一间距的第二间距彼此间隔开，将蚀刻速率调节掺杂剂注入所述第二区域以形成注入区域， 同时阻挡第一区域，通过蚀刻多个第一栅极之间的第一区域形成第一沟槽，并且通过蚀刻多个第二栅极之间的第二区域形成第二沟槽。