公开(公告)号：US10199471B2

公开(公告)日：2019-02-05

申请号：US15059519

申请日：2016-03-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyoseok Choi ,  Hwichan Jun ,  Yoonhae Kim ,  Chulsung Kim ,  Heungsik Park ,  Doo-Young Lee

IPC: H01L29/417 ,  H01L29/78 ,  H01L29/66

Abstract: Provided is a semiconductor device including a substrate with an active pattern, a gate electrode crossing the active pattern, a source/drain region in an upper portion of the active pattern at a side of the gate electrode, the source/drain region including a recess region at an upper region thereof, a contact electrically connected to the source/drain region, the contact including a lower portion provided in the recess region, and a metal silicide layer provided at a lower region of the recess region and between the source/drain region and the contact.

公开(公告)号：US10056375B2

公开(公告)日：2018-08-21

申请号：US15687929

申请日：2017-08-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Doo-Young Lee ,  Sang-Hyun Lee ,  Myung-Hoon Jung ,  Do-Hyoung Kim

IPC: H01L21/00 ,  H01L27/088 ,  H01L21/768 ,  H01L21/28 ,  H01L29/45 ,  H01L29/417 ,  H01L27/02 ,  H01L21/8234 ,  H01L29/78 ,  H01L27/11

CPC classification number: H01L27/088 ,  H01L21/28114 ,  H01L21/76804 ,  H01L21/76805 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76897 ,  H01L21/823425 ,  H01L21/823475 ,  H01L23/485 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/1104 ,  H01L29/41758 ,  H01L29/41775 ,  H01L29/45 ,  H01L29/78

Abstract: A semiconductor device includes a first gate pattern and a second gate pattern on a substrate, the first gate pattern having a first height and the second gate pattern having a second height, an insulating pattern on the substrate covering the first and second gate patterns, the insulating pattern including a trench exposing the substrate between the first and second gate patterns, a spacer contacting at least a portion of a sidewall of the insulating pattern within the trench, the spacer spaced apart from the first and second gate patterns and having a third height larger than the first and second heights, and a contact structure filling the trench.

公开(公告)号：US09704745B2

公开(公告)日：2017-07-11

申请号：US14955374

申请日：2015-12-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： KeunHee Bai ,  Dohyoung Kim ,  Johnsoo Kim ,  Heungsik Park ,  Doo-Young Lee ,  Sanghyun Lee

IPC: H01L21/02 ,  H01L21/768 ,  H01L29/51 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L21/76897 ,  H01L21/823431 ,  H01L21/823475 ,  H01L29/517 ,  H01L29/66545

Abstract: A sacrificial layer is formed to cover the gate structures. The sacrificial layer is patterned to form a first opening in the sacrificial layer. A preliminary contact is formed in the first opening and the sacrificial layer is selectively removed. An insulating layer is formed to cover the gate structures and to expose the preliminary contact. The preliminary contact is removed to form a second opening in the insulating layer, and then a contact is formed in the second opening.

公开(公告)号：US11133392B2

公开(公告)日：2021-09-28

申请号：US16243564

申请日：2019-01-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyoseok Choi ,  Hwichan Jun ,  Yoonhae Kim ,  Chulsung Kim ,  Heungsik Park ,  Doo-Young Lee

IPC: H01L29/417 ,  H01L29/78 ,  H01L29/66

Abstract: Provided is a semiconductor device including a substrate with an active pattern, a gate electrode crossing the active pattern, a source/drain region in an upper portion of the active pattern at a side of the gate electrode, the source/drain region including a recess region at an upper region thereof, a contact electrically connected to the source/drain region, the contact including a lower portion provided in the recess region, and a metal silicide layer provided at a lower region of the recess region and between the source/drain region and the contact.

公开(公告)号：US09536983B2

公开(公告)日：2017-01-03

申请号：US14970710

申请日：2015-12-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Doo-Young Lee ,  Dohyoung Kim ,  Johnsoo Kim ,  Heungsik Park ,  Hongsik Shin ,  Younghun Choi

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/40

CPC classification number: H01L29/6656 ,  H01L29/401 ,  H01L29/4232 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of forming a semiconductor device includes forming a gate electrode on a substrate, forming a first spacer on a sidewall of the gate electrode, forming a second spacer on the first spacer, and forming a capping pattern on top surfaces of the gate electrode, the first spacer and the second spacer. An outer sidewall of the second spacer is vertically aligned with a sidewall of the capping pattern.

Abstract translation: 形成半导体器件的方法包括在衬底上形成栅电极，在栅电极的侧壁上形成第一间隔物，在第一间隔物上形成第二间隔物，并在栅电极的顶表面上形成封盖图案， 第一间隔物和第二间隔物。 第二间隔件的外侧壁与封盖图案的侧壁垂直对齐。

公开(公告)号：US20160233310A1

公开(公告)日：2016-08-11

申请号：US14970710

申请日：2015-12-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Doo-Young Lee ,  Dohyoung KIM ,  Johnsoo KIM ,  Heungsik PARK ,  Hongsik SHIN ,  Younghun CHOI

IPC: H01L29/66 ,  H01L29/40 ,  H01L29/423

CPC classification number: H01L29/6656 ,  H01L29/401 ,  H01L29/4232 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of forming a semiconductor device includes forming a gate electrode on a substrate, forming a first spacer on a sidewall of the gate electrode, forming a second spacer on the first spacer, and forming a capping pattern on top surfaces of the gate electrode, the first spacer and the second spacer. An outer sidewall of the second spacer is vertically aligned with a sidewall of the capping pattern.

Abstract translation: 形成半导体器件的方法包括在衬底上形成栅电极，在栅电极的侧壁上形成第一间隔物，在第一间隔物上形成第二间隔物，并在栅电极的顶表面上形成封盖图案， 第一间隔物和第二间隔物。 第二间隔件的外侧壁与封盖图案的侧壁垂直对齐。