公开(公告)号：US11302585B2

公开(公告)日：2022-04-12

申请号：US16810937

申请日：2020-03-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Min-Chul Sun ,  Myeong-Cheol Kim ,  Kyoung-Sub Shin

IPC: H01L21/8238 ,  H01L29/66 ,  H01L21/306 ,  H01L21/308 ,  H01L27/092 ,  H01L29/10 ,  H01L29/08 ,  H01L29/06 ,  H01L23/535 ,  H01L29/417 ,  H01L21/8234 ,  H01L27/088 ,  G06F7/505 ,  G06F30/39 ,  G06F30/398 ,  G06F119/12 ,  G06F117/12

Abstract: In a method of manufacturing a semiconductor device, first to third active fins are formed on a substrate. Each of the first to third active fins extends in a first direction, and the second active fin, the first active fin, and the third active fin are disposed in this order in a second direction crossing the first direction. The second active fin is removed using a first etching mask covering the first and third active fins. The third active fin is removed using a second etching mask covering the first active fin and a portion of the substrate from which the second active fin is removed. A first gate structure is formed on the first active fin. A first source/drain layer is formed on a portion of the first active fin adjacent the first gate structure.

公开(公告)号：US09653363B2

公开(公告)日：2017-05-16

申请号：US15167050

申请日：2016-05-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Bok-Young Lee ,  Jeong-Yun Lee ,  Dong-Hyun Kim ,  Myeong-Cheol Kim ,  Dong-Woo Han

IPC: H01L21/336 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/02 ,  H01L21/306 ,  H01L29/66

CPC classification number: H01L21/823821 ,  H01L21/30604 ,  H01L21/823828 ,  H01L27/0207 ,  H01L27/0886 ,  H01L29/6656 ,  H01L29/66795

Abstract: Provided are a semiconductor device and a method of fabricating a semiconductor device. The semiconductor device includes a first active fin and a second active fin which protrude from a substrate and extend along a first direction, a first gate structure which is on the first active fin to extend along a second direction intersecting the first direction, a second gate structure which is located adjacent to the first gate structure in the second direction and is on the second active fin to extend along the second direction, and a dummy structure which is in a space between the first gate structure and the second gate structure.

公开(公告)号：US09305921B2

公开(公告)日：2016-04-05

申请号：US14565903

申请日：2014-12-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Chan Lee ,  Seung-Jae Lee ,  Sang-Bom Kang ,  Dae-Young Kwak ,  Myeong-Cheol Kim ,  Yong-Ho Jeon

IPC: H01L31/058 ,  H01L27/088 ,  H01L21/764 ,  H01L27/11 ,  H01L27/12

CPC classification number: H01L27/088 ,  H01L21/764 ,  H01L27/0886 ,  H01L27/1116 ,  H01L27/1211

Abstract: A semiconductor device including: a first gate pattern disposed in a peripheral region of a substrate; a second gate pattern disposed in a cell region of the substrate; a first insulator formed on sidewalls of the first gate pattern; and a second insulator formed on sidewalls of the second gate pattern, wherein a dielectric constant of the first insulator is different from a dielectric constant of the second insulator, and wherein a height of the second insulator is greater than a height of the second gate pattern.

Abstract translation: 一种半导体器件，包括：设置在衬底的周边区域中的第一栅极图案; 设置在所述基板的单元区域中的第二栅极图案; 形成在第一栅极图案的侧壁上的第一绝缘体; 以及形成在所述第二栅极图案的侧壁上的第二绝缘体，其中所述第一绝缘体的介电常数不同于所述第二绝缘体的介电常数，并且其中所述第二绝缘体的高度大于所述第二栅极图案的高度 。

公开(公告)号：US09299811B2

公开(公告)日：2016-03-29

申请号：US14519771

申请日：2014-10-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wook-Je Kim ,  Jae-Yup Chung ,  Jong-Seo Hong ,  Cheol Kim ,  Hee-Soo Kang ,  Hyun-Jo Kim ,  Hee-Don Jeong ,  Soo-Hun Hong ,  Sang-Bom Kang ,  Myeong-Cheol Kim ,  Young-Su Chung

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/165

CPC classification number: H01L29/66795 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/7848

Abstract: Semiconductor devices may include first and second fins that protrude from a substrate, extend in a first direction, and are separated from each other in the first direction. Semiconductor devices may also include a field insulating layer that is disposed between the first and second fins to extend in a second direction intersecting the first direction, an etch-stop layer pattern that is formed on the field insulating layer and a dummy gate structure that is formed on the etch-stop layer pattern.

Abstract translation: 半导体器件可以包括从基板突出的第一和第二鳍片，沿第一方向延伸，并且在第一方向上彼此分离。 半导体器件还可以包括场绝缘层，其设置在第一和第二鳍之间，沿与第一方向相交的第二方向延伸，形成在场绝缘层上的蚀刻停止层图案和伪栅极结构， 形成在蚀刻停止层图案上。

公开(公告)号：US20150147860A1

公开(公告)日：2015-05-28

申请号：US14519771

申请日：2014-10-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wook-Je Kim ,  Jae-Yup Chung ,  Jong-Seo Hong ,  Cheol Kim ,  Hee-Soo Kang ,  Hyun-Jo Kim ,  Hee-Don Jeong ,  Soo-Hun Hong ,  Sang-Bom Kang ,  Myeong-Cheol Kim ,  Young-Su Chung

IPC: H01L29/66

CPC classification number: H01L29/66795 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/7848

Abstract: Semiconductor devices may include first and second fins that protrude from a substrate, extend in a first direction, and are separated from each other in the first direction. Semiconductor devices may also include a field insulating layer that is disposed between the first and second fins to extend in a second direction intersecting the first direction, an etch-stop layer pattern that is formed on the field insulating layer and a dummy gate structure that is formed on the etch-stop layer pattern.

Abstract translation: 半导体器件可以包括从基板突出的第一和第二鳍片，沿第一方向延伸，并且在第一方向上彼此分离。 半导体器件还可以包括场绝缘层，其设置在第一和第二鳍之间，沿与第一方向相交的第二方向延伸，形成在场绝缘层上的蚀刻停止层图案和伪栅极结构， 形成在蚀刻停止层图案上。

公开(公告)号：US08946069B2

公开(公告)日：2015-02-03

申请号：US14138721

申请日：2013-12-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-Wook Lee ,  Myeong-Cheol Kim ,  Sang-Min Lee ,  Young-Ju Park ,  Hyung-Yong Kim ,  Myung-Hoon Jung

IPC: H01L21/336 ,  H01L29/66 ,  H01L21/265 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/78

CPC classification number: H01L29/7848 ,  H01L21/26506 ,  H01L21/30608 ,  H01L21/3065 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/11 ,  H01L29/66636 ,  H01L29/78

Abstract: A fabricating method of a semiconductor device includes providing a substrate having a first region and a second region, forming a plurality of first gates in the first region of the substrate, such that the first gates are spaced apart from each other at a first pitch, forming a plurality of second gates in the second region of the substrate, such that the second gates are spaced apart from each other at a second pitch different from the first pitch, implanting an etch rate adjusting dopant into the second region to form implanted regions, while blocking the first region, forming a first trench by etching the first region between the plurality of first gates, and forming a second trench by etching the second region between the plurality of second gates.

Abstract translation: 半导体器件的制造方法包括提供具有第一区域和第二区域的衬底，在衬底的第一区域中形成多个第一栅极，使得第一栅极以第一间距相互间隔开， 在所述衬底的所述第二区域中形成多个第二栅极，使得所述第二栅极以不同于所述第一间距的第二间距彼此间隔开，将蚀刻速率调节掺杂剂注入所述第二区域以形成注入区域， 同时阻挡第一区域，通过蚀刻多个第一栅极之间的第一区域形成第一沟槽，并且通过蚀刻多个第二栅极之间的第二区域形成第二沟槽。

公开(公告)号：US12261087B2

公开(公告)日：2025-03-25

申请号：US18491470

申请日：2023-10-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Min-Chul Sun ,  Myeong-Cheol Kim ,  Kyoung-Sub Shin

IPC: H01L29/10 ,  G06F7/505 ,  G06F30/39 ,  G06F30/398 ,  H01L21/306 ,  H01L21/308 ,  H01L21/8234 ,  H01L21/8238 ,  H01L23/535 ,  H01L27/088 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66 ,  G06F117/12 ,  G06F119/12

Abstract: In a method of manufacturing a semiconductor device, first to third active fins are formed on a substrate. Each of the first to third active fins extends in a first direction, and the second active fin, the first active fin, and the third active fin are disposed in this order in a second direction crossing the first direction. The second active fin is removed using a first etching mask covering the first and third active fins. The third active fin is removed using a second etching mask covering the first active fin and a portion of the substrate from which the second active fin is removed. A first gate structure is formed on the first active fin. A first source/drain layer is formed on a portion of the first active fin adjacent the first gate structure.

公开(公告)号：US10109532B2

公开(公告)日：2018-10-23

申请号：US15658964

申请日：2017-07-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Min-Chul Sun ,  Myeong-Cheol Kim ,  Kyoung-Sub Shin

IPC: H01L21/8238 ,  H01L29/66 ,  H01L21/306 ,  H01L21/308 ,  H01L27/092 ,  H01L29/10 ,  H01L29/08 ,  H01L29/06 ,  H01L23/535 ,  G06F7/505 ,  G06F17/50

Abstract: In a method of manufacturing a semiconductor device, first to third active fins are formed on a substrate. Each of the first to third active fins extends in a first direction, and the second active fin, the first active fin, and the third active fin are disposed in this order in a second direction crossing the first direction. The second active fin is removed using a first etching mask covering the first and third active fins. The third active fin is removed using a second etching mask covering the first active fin and a portion of the substrate from which the second active fin is removed. A first gate structure is formed on the first active fin. A first source/drain layer is formed on a portion of the first active fin adjacent the first gate structure.

公开(公告)号：US09627542B2

公开(公告)日：2017-04-18

申请号：US15144662

申请日：2016-05-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byoung-Ho Kwon ,  Cheol Kim ,  Ho-Young Kim ,  Se-Jung Park ,  Myeong-Cheol Kim ,  Bo-Kyeong Kang ,  Bo-Un Yoon ,  Jae-Kwang Choi ,  Si-Young Choi ,  Suk-Hoon Jeong ,  Geum-Jung Seong ,  Hee-Don Jeong ,  Yong-Joon Choi ,  Ji-Eun Han

IPC: H01L29/78 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/308 ,  H01L29/423 ,  H01L21/84 ,  H01L27/12 ,  H01L21/8238 ,  H01L29/49

CPC classification number: H01L29/7853 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/3085 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/42364 ,  H01L29/4238 ,  H01L29/49 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785

Abstract: Semiconductor devices may include a semiconductor substrate with a first semiconductor fin aligned end-to-end with a second semiconductor with a recess between facing ends of the first and second semiconductor fins. A first insulator pattern is formed adjacent sidewalls of the first and second semiconductor fins and a second insulator pattern is formed within the first recess. The second insulator pattern may have a top surface higher than a top surface of the first insulator pattern, such as to the height of the top surface of the fins (or higher or lower). First and second gates extend along sidewalls and a top surface of the first semiconductor fin. A dummy gate electrode may be formed on the top surface of the second insulator. Methods for manufacture of the same and modifications are also disclosed.

公开(公告)号：US09401359B2

公开(公告)日：2016-07-26

申请号：US14553665

申请日：2014-11-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Soo-Yeon Jeong ,  Myeong-Cheol Kim ,  Do-Hyoung Kim ,  Do-Haing Lee ,  Nam-Myun Cho ,  In-Ho Kim

IPC: H01L21/02 ,  H01L27/088 ,  H01L21/768 ,  H01L21/285 ,  H01L29/49 ,  H01L29/66 ,  H01L29/45

CPC classification number: H01L27/088 ,  H01L21/28518 ,  H01L21/76897 ,  H01L29/45 ,  H01L29/49 ,  H01L29/66545

Abstract: A method of manufacturing a semiconductor device includes forming a gate structure through a first insulating interlayer on a substrate such that the gate structure includes a spacer on a sidewall thereof, forming a first hard mask on the gate structure, partially removing the first insulating interlayer using the first hard mask as an etching mask to form a first contact hole such that the first contact hole exposes a top surface of the substrate, forming a metal silicide pattern on the top surface of the substrate exposed by the first contact hole, and forming a plug electrically connected to the metal silicide pattern.

Abstract translation: 一种制造半导体器件的方法包括通过基板上的第一绝缘中间层形成栅极结构，使得栅极结构在其侧壁上包括间隔物，在栅极结构上形成第一硬掩模，使用 所述第一硬掩模作为蚀刻掩模以形成第一接触孔，使得所述第一接触孔暴露所述基板的顶表面，在所述基板的由所述第一接触孔暴露的所述顶表面上形成金属硅化物图案，并形成 插头电连接到金属硅化物图案。