公开(公告)号：US12190964B2

公开(公告)日：2025-01-07

申请号：US17750315

申请日：2022-05-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanggi Hong ,  Chaehoon Kim ,  Sangwon Park ,  Jiho Cho

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24

Abstract: In a method of operating a nonvolatile memory device that includes a memory block including cell strings where each of the cell strings includes a string selection transistor, memory cells and a ground selection transistor which are connected in series and disposed in a vertical direction, each of word-lines coupled to the memory cells is set up to a respective target level during a word-line set-up period, a sensing operation on target memory cells is performed by applying a read voltage to a selected word-line coupled to the target memory cells while applying a read pass voltage to unselected word-lines during a sensing period, and while consuming an internal voltage connected to the unselected word-lines in a particular circuit in the nonvolatile memory device, a voltage level of the unselected word-lines is recovered to a level of the internal voltage during a discharge period of a word-line recovery period.

公开(公告)号：US12062395B2

公开(公告)日：2024-08-13

申请号：US17750642

申请日：2022-05-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yohan Lee ,  Chaehoon Kim ,  Jungyun Yun ,  Jiho Cho ,  Sanggi Hong

IPC: G11C16/14 ,  G11C16/04 ,  G11C16/08 ,  G11C16/30 ,  G11C11/56 ,  G11C16/34

CPC classification number: G11C16/14 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/30 ,  G11C11/5628 ,  G11C16/3445 ,  G11C16/3459

Abstract: A nonvolatile memory device includes a memory block and a control circuit. The memory block includes a plurality of cell strings where each of the plurality of cell strings includes a string selection transistor, a plurality of memory cells and a ground selection transistor which are connected in series and disposed in a vertical direction between a bit-line and a common source line. The control circuit adjusts a level of a high voltage applied to a gate of a pass transistor of a selected word-line such that a voltage difference between the high voltage and a program voltage applied to a drain of the pass transistor differs in at least a portion of a plurality of program loops based on a comparison of a number of the program loops and a reference number during a program operation on a target memory cells.