USER DEVICE INCLUDING A NONVOLATILE MEMORY DEVICE AND A DATA WRITE METHOD THEREOF

    公开(公告)号:US20210357319A1

    公开(公告)日:2021-11-18

    申请号:US17386782

    申请日:2021-07-28

    Abstract: An access method of a nonvolatile memory device included in a user device includes receiving a write request to write data into the nonvolatile memory device; detecting an application issuing the write request, a user context, a queue size of a write buffer, an attribute of the write-requested data, or an operation mode of the user device; and deciding one of a plurality of write modes to use for writing the write-requested data into the nonvolatile memory device according to the detected information. The write modes have different program voltages and verify voltage sets.

    USER DEVICE INCLUDING A NONVOLATILE MEMORY DEVICE AND A DATA WRITE METHOD THEREOF

    公开(公告)号:US20200278926A1

    公开(公告)日:2020-09-03

    申请号:US16877802

    申请日:2020-05-19

    Abstract: An access method of a nonvolatile memory device included in a user device includes receiving a write request to write data into the nonvolatile memory device; detecting an application issuing the write request, a user context, a queue size of a write buffer, an attribute of the write-requested data, or an operation mode of the user device; and deciding one of a plurality of write modes to use for writing the write-requested data into the nonvolatile memory device according to the detected information. The write modes have different program voltages and verify voltage sets.

    STORAGE DEVICE HAVING FAST CELL INFORMATION AND OPERATION METHOD THEREOF

    公开(公告)号:US20250068559A1

    公开(公告)日:2025-02-27

    申请号:US18590574

    申请日:2024-02-28

    Abstract: A storage device includes a non-volatile memory device configured to store fast cell information obtained from a threshold voltage distribution formed through a one-shot program for memory cells; and a storage controller configured to read the fast cell information from the non-volatile memory device during booting or initialization to perform mapping a fast cell area based on a fast cell management policy, wherein the fast cell information is acquired through the one-shot program performed in a test stage or a mass production evaluation stage, and is stored in the non-volatile memory device before a firmware of the storage controller is executed.

    STORAGE DEVICE AND OPERATION METHOD THEREOF

    公开(公告)号:US20250060885A1

    公开(公告)日:2025-02-20

    申请号:US18421352

    申请日:2024-01-24

    Abstract: A storage device according to an embodiment includes a memory device configured to apply a first program voltage and a first verification voltage to a first word line and output, based on a program state of each of a plurality of memory cells connected to the first word line, a speed information representing a speed characteristic of each of the plurality of memory cells; and a memory controller configured to determine at least one memory cell to be programmed into a predetermined program state; determine, among the at least one memory cell, at least one target memory cell having a first speed characteristic based on the speed information; and perform a state-shaping operation to convert a data corresponding to the predetermined program state for the at least one target memory cell into a value corresponding to a program state different from the predetermined program state.

    NONVOLATILE MEMORY DEVICE AND OPERATION METHOD THEREOF

    公开(公告)号:US20250061937A1

    公开(公告)日:2025-02-20

    申请号:US18934502

    申请日:2024-11-01

    Abstract: Disclosed is a nonvolatile memory device which include a memory cell array including a plurality of memory cells connected to a plurality of word lines, an address decoder that controls a selected word line among the plurality of word lines based on an address received from an external device including a first temperature sensor, a second temperature sensor that measures a read temperature of first memory cells connected to the selected word line from among the plurality of memory cells, and a temperature compensation circuit that calculates a read level offset based on the read temperature and a program temperature of the first memory cells measured by the first temperature sensor and generates a compensation read voltage based on the read level offset. The address decoder is further configured to provide the compensation read voltage to the selected word line.

    OPERATION METHOD OF STORAGE CONTROLLER FOR NONVOLATILE MEMORY DEVICE

    公开(公告)号:US20240176700A1

    公开(公告)日:2024-05-30

    申请号:US18512613

    申请日:2023-11-17

    CPC classification number: G06F11/1068 G06F11/076

    Abstract: An operation method of a storage controller, which is configured to control a nonvolatile memory device, includes initiating a first instance of a respective reliability operation for a respective memory block included in the nonvolatile memory device, the respective reliability operation including detecting a degradation level of the respective memory block and setting a respective skip reference value based on the detected degradation level; determining whether a respective number of consecutively skipped instances of the respective reliability operation is less than the respective skip reference value; and selectively skipping or performing a next instance of the respective reliability operation based on the determination result.

Patent Agency Ranking