公开(公告)号：US09627542B2

公开(公告)日：2017-04-18

申请号：US15144662

申请日：2016-05-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byoung-Ho Kwon ,  Cheol Kim ,  Ho-Young Kim ,  Se-Jung Park ,  Myeong-Cheol Kim ,  Bo-Kyeong Kang ,  Bo-Un Yoon ,  Jae-Kwang Choi ,  Si-Young Choi ,  Suk-Hoon Jeong ,  Geum-Jung Seong ,  Hee-Don Jeong ,  Yong-Joon Choi ,  Ji-Eun Han

IPC: H01L29/78 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/308 ,  H01L29/423 ,  H01L21/84 ,  H01L27/12 ,  H01L21/8238 ,  H01L29/49

CPC classification number: H01L29/7853 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/3085 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/42364 ,  H01L29/4238 ,  H01L29/49 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785

Abstract: Semiconductor devices may include a semiconductor substrate with a first semiconductor fin aligned end-to-end with a second semiconductor with a recess between facing ends of the first and second semiconductor fins. A first insulator pattern is formed adjacent sidewalls of the first and second semiconductor fins and a second insulator pattern is formed within the first recess. The second insulator pattern may have a top surface higher than a top surface of the first insulator pattern, such as to the height of the top surface of the fins (or higher or lower). First and second gates extend along sidewalls and a top surface of the first semiconductor fin. A dummy gate electrode may be formed on the top surface of the second insulator. Methods for manufacture of the same and modifications are also disclosed.

公开(公告)号：US10062786B2

公开(公告)日：2018-08-28

申请号：US15168694

申请日：2016-05-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju-Hyun Kim ,  Ho-Young Kim ,  Se-Jung Park ,  Bo-Un Yoon

IPC: H01L27/088 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L21/762

CPC classification number: H01L29/7856 ,  H01L21/76229 ,  H01L21/76232 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66795 ,  H01L29/7853 ,  H01L29/7854

Abstract: A semiconductor device includes a first fin-type pattern on a substrate, having a first sidewall and a second sidewall opposed to each other; a first trench formed in contact with the first sidewall; a second trench formed in contact with the second sidewall; a first field insulating layer partially filling the first trench; and a second field insulating layer partially filling the second trench and a second field insulating layer partially filling the second trench. The second field insulating layer includes a first region and a second region disposed in a sequential order starting from the second sidewall, an upper surface of the second region being higher than an upper surface of the first field insulating layer. The device further includes a gate electrode on the first fin-type pattern, the first field insulating layer and the second field insulating layer, the gate electrode intersecting the first fin-type pattern and overlapping the second region.