公开(公告)号：US09627542B2

公开(公告)日：2017-04-18

申请号：US15144662

申请日：2016-05-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byoung-Ho Kwon ,  Cheol Kim ,  Ho-Young Kim ,  Se-Jung Park ,  Myeong-Cheol Kim ,  Bo-Kyeong Kang ,  Bo-Un Yoon ,  Jae-Kwang Choi ,  Si-Young Choi ,  Suk-Hoon Jeong ,  Geum-Jung Seong ,  Hee-Don Jeong ,  Yong-Joon Choi ,  Ji-Eun Han

IPC: H01L29/78 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/308 ,  H01L29/423 ,  H01L21/84 ,  H01L27/12 ,  H01L21/8238 ,  H01L29/49

CPC classification number: H01L29/7853 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/3085 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/42364 ,  H01L29/4238 ,  H01L29/49 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785

Abstract: Semiconductor devices may include a semiconductor substrate with a first semiconductor fin aligned end-to-end with a second semiconductor with a recess between facing ends of the first and second semiconductor fins. A first insulator pattern is formed adjacent sidewalls of the first and second semiconductor fins and a second insulator pattern is formed within the first recess. The second insulator pattern may have a top surface higher than a top surface of the first insulator pattern, such as to the height of the top surface of the fins (or higher or lower). First and second gates extend along sidewalls and a top surface of the first semiconductor fin. A dummy gate electrode may be formed on the top surface of the second insulator. Methods for manufacture of the same and modifications are also disclosed.

公开(公告)号：US20170098653A1

公开(公告)日：2017-04-06

申请号：US15182637

申请日：2016-06-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-Ho Koh ,  Hye-Sung Park ,  Byoung-Ho Kwon ,  Jong-Hyuk Park ,  Bo-Un Yoon ,  ln-Seak Hwang

IPC: H01L27/108 ,  H01L21/311 ,  H01L21/3105

CPC classification number: H01L27/10894 ,  H01L21/31053 ,  H01L21/31056 ,  H01L21/31138 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10855 ,  H01L27/10897

Abstract: Methods of manufacturing a semiconductor device are provided. Methods may include forming first to third regions having densities different from one another on a substrate, covering the first to third regions to form an upper interlayer insulating film including a low step portion and a high step portion higher than the low step portion, forming an organic film on the upper interlayer insulating film, removing a part of the organic film to expose an upper surface of the high step portion, removing the high step portion so that an upper surface of the high step portion is disposed on at least the same line as the organic film disposed on the upper surface of the lower step portion, removing the remaining part of the organic film to expose the upper surface of the upper interlayer insulating film and flattening the upper surface of the upper interlayer insulating film.

公开(公告)号：US09960169B2

公开(公告)日：2018-05-01

申请号：US15243248

申请日：2016-08-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun-Seok Lee ,  Byoung-Ho Kwon ,  Sang-Kyun Kim ,  Yun-Jeong Kim ,  Seung-Ho Park ,  Hao Cui ,  In-Seak Hwang

IPC: H01L27/108 ,  H01L21/762 ,  H01L21/3105

CPC classification number: H01L27/10873 ,  H01L21/0337 ,  H01L21/31053 ,  H01L21/31058 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/76224 ,  H01L21/76229 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10894

Abstract: In a method of manufacturing a semiconductor device, mask patterns are formed on a semiconductor substrate. An organic layer is formed on the semiconductor substrate to cover the mask patterns. An upper portion of the organic layer is planarized using a polishing composition. The polishing composition includes an oxidizing agent and is devoid of abrasive particles.

公开(公告)号：US20170062437A1

公开(公告)日：2017-03-02

申请号：US15243248

申请日：2016-08-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun-Seok Lee ,  Byoung-Ho Kwon ,  Sang-Kyun Kim ,  Yun-Jeong Kim ,  Seung-Ho Park ,  Hao Cui ,  ln-Seak Hwang

IPC: H01L27/108 ,  H01L21/3105 ,  H01L21/762

CPC classification number: H01L27/10873 ,  H01L21/0337 ,  H01L21/31053 ,  H01L21/31058 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/76224 ,  H01L21/76229 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10894

Abstract: In a method of manufacturing a semiconductor device, mask patterns are formed on a semiconductor substrate. An organic layer is formed on the semiconductor substrate to cover the mask patterns. An upper portion of the organic layer is planarized using a polishing composition. The polishing composition includes an oxidizing agent and is devoid of abrasive particles.

Abstract translation: 在制造半导体器件的方法中，在半导体衬底上形成掩模图案。 在半导体衬底上形成有机层以覆盖掩模图案。 使用抛光组合物对有机层的上部进行平面化处理。 抛光组合物包括氧化剂并且没有磨料颗粒。