公开(公告)号：US20240130123A1

公开(公告)日：2024-04-18

申请号：US18208459

申请日：2023-06-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yejin PARK ,  Seung Yoon KIM ,  Heesuk KIM ,  Hyeongjin KIM ,  Sehee JANG ,  Minsoo SHIN ,  Seungjun SHIN ,  Sanghun CHUN ,  Jeehoon HAN ,  Jae-Hwang SIM ,  Jongseon AHN

IPC: H10B43/27 ,  H01L23/522 ,  H01L23/528 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35 ,  H10B80/00

CPC classification number: H10B43/27 ,  H01L23/5226 ,  H01L23/5283 ,  H01L25/0652 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35 ,  H10B80/00 ,  H01L2225/06541

Abstract: Disclosed are semiconductor devices, electronic systems including the same, and methods of fabricating the same. The semiconductor device comprises a first gate stack structure including a first dielectric pattern and a first conductive pattern that are alternately stacked with each other, a memory channel structure including a first memory portion that penetrates the first gate stack structure, a through contact including a first through portion at a level the same as a level of the first memory portion, and a connection contact including a first connection portion at a level the same as the level of the first memory portion and the level of the first through portion. A minimum width of the first memory portion is less than a minimum width of the first through portion and a minimum width of the first connection portion.

公开(公告)号：US20240215252A1

公开(公告)日：2024-06-27

申请号：US18481404

申请日：2023-10-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanghun CHUN ,  Sehee JANG ,  Jeehoon HAN

IPC: H10B43/40 ,  G11C16/04 ,  H01L23/528 ,  H01L25/065 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00

CPC classification number: H10B43/40 ,  G11C16/0483 ,  H01L23/5283 ,  H01L25/0652 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00 ,  H01L2225/06506

Abstract: A nonvolatile memory device includes a peripheral circuit structure including a peripheral circuit and a first insulating structure covering the peripheral circuit and a cell array structure bonded to the peripheral circuit structure and including a cell region and a connection region, wherein the cell array structure includes a common source line layer, a buffer insulating layer on the common source line layer, a plurality of contact stop layers buried in the buffer insulating layer, a cell stack which includes a plurality of gate electrodes and a plurality of insulating layers alternately stacked on the buffer insulating layer, a plurality of cell channel structures extending to the common source line layer by passing through the cell stack, a plurality of contact structures each connected to one or more of the plurality of gate electrodes, and a second insulating structure covering the cell stack.