公开(公告)号：US20240413125A1

公开(公告)日：2024-12-12

申请号：US18677392

申请日：2024-05-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seho You ,  Sangcheon Park

IPC: H01L25/065 ,  G02B6/42 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L25/07

Abstract: Provided is a semiconductor package including a package substrate, a connection substrate mounted on the package substrate, and including a first conductive connection structure, a first integrated circuit device mounted on the package substrate, and a second integrated circuit device disposed on the connection substrate and the first integrated circuit device, and including a first portion overlapping the first integrated circuit device and a second portion overlapping the connection substrate, wherein one of the first integrated circuit device and the second integrated circuit device includes a photonic integrated circuit device to which an optical fiber is attached, and the other of the first integrated circuit device and the second integrated circuit device includes an electronic integrated circuit device, and wherein the second integrated circuit device is electrically connected to the package substrate via the first conductive connection structure of the connection substrate.

公开(公告)号：US20230057342A1

公开(公告)日：2023-02-23

申请号：US18048825

申请日：2022-10-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： EUNSEOK SONG ,  Kyungsuk Oh ,  Seho You

IPC: H01L25/18 ,  H01L23/00 ,  H01L23/48

Abstract: A semiconductor package includes a package substrate, a logic chip stacked on the package substrate and including at least one logic element, and a stack structure. The stack structure includes an integrated voltage regulator (IVR) chip including a voltage regulating circuit that regulates a voltage of the at least one logic element, and a passive element chip stacked on the IVR chip and including an inductor.

公开(公告)号：US20250015046A1

公开(公告)日：2025-01-09

申请号：US18661640

申请日：2024-05-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seho You ,  Kyungdon Mun

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/522 ,  H10B80/00

Abstract: A semiconductor package includes a package substrate including first and second wirings, a logic chip on the package substrate, electrically connected to the first wiring, and including a first wireless communication element, a chip structure on the logic chip, and including a buffer chip containing first and second through-electrodes, a first connection circuit electrically connected to the first through-electrode, and a second connection circuit electrically connected to the second through-electrode, and a plurality of memory chips stacked on the buffer chip and electrically connected to the first and second through-electrodes, a second wireless communication element within the buffer chip or between the buffer chip and the logic chip, electrically connected to the first connection circuit, and coupled to the first wireless communication element, and a plurality of conductive vertical structures between the chip structure and the package substrate and electrically connecting the second connection circuit and the second wiring.

公开(公告)号：US11670629B2

公开(公告)日：2023-06-06

申请号：US17190689

申请日：2021-03-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seho You ,  Kyounglim Suk

IPC: H01L25/18 ,  H01L23/498 ,  H01L23/522 ,  H01L23/31 ,  H01L23/00 ,  H01L23/48 ,  H01L23/66

CPC classification number: H01L25/18 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/5226 ,  H01L23/66 ,  H01L24/20 ,  H01L24/16 ,  H01L2223/6677 ,  H01L2224/16227

Abstract: A semiconductor package is provided. The semiconductor package comprising a first redistribution structure comprising a first redistribution pattern; a first semiconductor chip on the first redistribution structure, the first semiconductor chip comprising a semiconductor substrate comprising a first surface and a second surface, a first back end of line (BEOL) structure on the first surface of the semiconductor substrate and comprising a first interconnect pattern, and a second BEOL structure on the second surface of the semiconductor substrate and comprising a second interconnect pattern; a molding layer covering a sidewall of the first semiconductor chip; a second redistribution structure on the first semiconductor chip and the molding layer and comprising a second redistribution pattern electrically connected to the second interconnect pattern.

公开(公告)号：US11482516B2

公开(公告)日：2022-10-25

申请号：US17002979

申请日：2020-08-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eunseok Song ,  Kyungsuk Oh ,  Seho You

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L25/18 ,  H01L23/00

Abstract: A semiconductor package includes a package substrate, a logic chip stacked on the package substrate and including at least one logic element, and a stack structure. The stack structure includes an integrated voltage regulator (IVR) chip including a voltage regulating circuit that regulates a voltage of the at least one logic element, and a passive element chip stacked on the IVR chip and including an inductor.

公开(公告)号：US12068302B2

公开(公告)日：2024-08-20

申请号：US18301420

申请日：2023-04-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seho You ,  Kyounglim Suk

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498 ,  H01L23/522 ,  H01L23/66 ,  H01L25/18

CPC classification number: H01L25/18 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/5226 ,  H01L23/5389 ,  H01L23/66 ,  H01L24/20 ,  H01L24/16 ,  H01L2223/6677 ,  H01L2224/16227

Abstract: A semiconductor package is provided. The semiconductor package comprising a first redistribution structure comprising a first redistribution pattern; a first semiconductor chip on the first redistribution structure, the first semiconductor chip comprising a semiconductor substrate comprising a first surface and a second surface, a first back end of line (BEOL) structure on the first surface of the semiconductor substrate and comprising a first interconnect pattern, and a second BEOL structure on the second surface of the semiconductor substrate and comprising a second interconnect pattern; a molding layer covering a sidewall of the first semiconductor chip; a second redistribution structure on the first semiconductor chip and the molding layer and comprising a second redistribution pattern electrically connected to the second interconnect pattern.

公开(公告)号：US11996398B2

公开(公告)日：2024-05-28

申请号：US18048825

申请日：2022-10-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eunseok Song ,  Kyungsuk Oh ,  Seho You

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/52 ,  H01L25/18 ,  H01L29/40

CPC classification number: H01L25/18 ,  H01L23/481 ,  H01L24/05 ,  H01L24/29 ,  H01L2224/05647 ,  H01L2924/1427 ,  H01L2924/1431

Abstract: A semiconductor package includes a package substrate, a logic chip stacked on the package substrate and including at least one logic element, and a stack structure. The stack structure includes an integrated voltage regulator (IVR) chip including a voltage regulating circuit that regulates a voltage of the at least one logic element, and a passive element chip stacked on the IVR chip and including an inductor.

公开(公告)号：US20220375884A1

公开(公告)日：2022-11-24

申请号：US17732709

申请日：2022-04-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seho You

IPC: H01L23/66 ,  H01L23/367 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56 ,  H01Q1/22 ,  H01Q21/00 ,  H01Q21/06

Abstract: A semiconductor package includes a semiconductor chip comprising an active surface and an inactive surface facing each other. At least one antenna module is arranged adjacent to the semiconductor chip. The at least one antenna module comprises a main antenna and a sub-antenna. A redistribution structure is disposed on the semiconductor chip and the at least one antenna module. The redistribution structure electrically connects the active surface of the semiconductor chip to the at least one antenna module. A molding member surrounds the semiconductor chip and the at least one antenna module. The inactive surface of the semiconductor chip and the main antenna are exposed from the molding member, and the sub-antenna is covered by the molding member.