公开(公告)号：US20170110177A1

公开(公告)日：2017-04-20

申请号：US15194784

申请日：2016-06-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-Ho LEE ,  Seung-Jun SHIN ,  Tae-Young OH

IPC: G11C11/406 ,  G06F3/06

CPC classification number: G11C11/40615 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0683 ,  G11C11/40618

Abstract: A memory device includes a memory bank including a plurality of memory blocks, a row selection circuit and a refresh controller. The row selection circuit is configured to perform an access operation and a refresh operation with respect to the memory bank. The refresh controller is configured to control the row selection circuit such that the memory device is operated selectively in an access mode or a self-refresh mode in response to a self-refresh command received from a memory controller, the refresh operation is performed in the access mode in response to an active command received from the memory controller and the refresh operation is performed in the self-refresh mode in response to at least one clock signal.

公开(公告)号：US20210358529A1

公开(公告)日：2021-11-18

申请号：US17387036

申请日：2021-07-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung-Jun SHIN ,  Tae-Young OH

IPC: G11C8/06 ,  G11C8/18 ,  G11C8/10 ,  G11C7/22 ,  G11C7/10 ,  G06F3/06 ,  G11C11/4076 ,  G06F13/16

Abstract: A memory system includes a memory controller and a memory. The memory controller selectively operates in a first mode and a second mode. In the first mode, the memory controller transmits a first command continuously during a plurality of clock cycles. In the second mode, the memory controller to mix a second command with the first command and transmit the mixture of the first command and the second command. The memory changes command latch timing depending on the first or second mode.

公开(公告)号：US20200278790A1

公开(公告)日：2020-09-03

申请号：US16874916

申请日：2020-05-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung-Jun SHIN ,  Tae-Young OH

IPC: G06F3/06 ,  G11C8/18 ,  G11C8/06 ,  G11C8/10 ,  G11C7/22 ,  G11C7/10 ,  G11C11/4076 ,  G06F13/16

Abstract: A memory system includes a memory controller and a memory. The memory controller selectively operates in a first mode and a second mode. In the first mode, the memory controller transmits a first command continuously during a plurality of clock cycles. In the second mode, the memory controller to mix a second command with the first command and transmit the mixture of the first command and the second command. The memory changes command latch timing depending on the first or second mode.

公开(公告)号：US20230410863A1

公开(公告)日：2023-12-21

申请号：US18238232

申请日：2023-08-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung-Jun SHIN ,  Tae-Young OH

IPC: G11C8/06 ,  G11C8/18 ,  G11C8/10 ,  G11C7/22 ,  G11C7/10 ,  G06F3/06 ,  G11C11/4076 ,  G06F13/16

CPC classification number: G11C8/06 ,  G11C8/18 ,  G11C8/10 ,  G11C7/22 ,  G11C7/1057 ,  G06F3/06 ,  G11C7/1045 ,  G11C11/4076 ,  G06F13/1689 ,  G11C7/10

Abstract: A memory system, including a memory controller and a memory, wherein the memory controller selectively operates in a first mode and a second mode. In the first mode, the memory controller transmits a first command continuously during a plurality of clock cycles. In the second mode, the memory controller mixes a second command with the first command and transmits the mixture of the first command and the second command. The memory changes command latch timing depends on the first or second mode.

公开(公告)号：US20170365309A1

公开(公告)日：2017-12-21

申请号：US15690379

申请日：2017-08-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung-Jun SHIN ,  Tae-Young OH

IPC: G11C7/22 ,  G11C8/18 ,  G11C7/10 ,  G06F3/06 ,  G11C8/06 ,  G11C11/4076 ,  G11C8/10

CPC classification number: G06F3/06 ,  G06F13/1689 ,  G11C7/10 ,  G11C7/1045 ,  G11C7/1057 ,  G11C7/22 ,  G11C8/06 ,  G11C8/10 ,  G11C8/18 ,  G11C11/4076

Abstract: A memory system includes a memory controller and a memory. The memory controller selectively operates in a first mode and a second mode. In the first mode, the memory controller transmits a first command continuously during a plurality of clock cycles. In the second mode, the memory controller to mix a second command with the first command and transmit the mixture of the first command and the second command. The memory changes command latch timing depending on the first or second mode.

公开(公告)号：US20170069364A1

公开(公告)日：2017-03-09

申请号：US15180175

申请日：2016-06-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung-Jun SHIN ,  Tae-Young OH

IPC: G11C8/18 ,  G11C8/10 ,  G11C8/06

CPC classification number: G06F3/06 ,  G06F13/1689 ,  G11C7/10 ,  G11C7/1045 ,  G11C7/1057 ,  G11C7/22 ,  G11C8/06 ,  G11C8/10 ,  G11C8/18 ,  G11C11/4076

Abstract: A memory system includes a memory controller and a memory. The memory controller selectively operates in a first mode and a second mode. In the first mode, the memory controller transmits a first command continuously during a plurality of clock cycles. In the second mode, the memory controller to mix a second command with the first command and transmit the mixture of the first command and the second command. The memory changes command latch timing depending on the first or second mode.

Abstract translation: 存储器系统包括存储器控制器和存储器。 存储器控制器选择性地以第一模式和第二模式操作。 在第一模式中，存储器控制器在多个时钟周期期间连续地发送第一命令。 在第二模式中，存储器控制器将第二命令与第一命令混合并传送第一命令和第二命令的混合。 存储器根据第一或第二模式改变命令锁存时序。

公开(公告)号：US20220351764A1

公开(公告)日：2022-11-03

申请号：US17862718

申请日：2022-07-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung-Jun SHIN ,  Tae-Young OH

IPC: G11C8/06 ,  G11C8/18 ,  G11C8/10 ,  G11C7/22 ,  G11C7/10 ,  G06F3/06 ,  G11C11/4076 ,  G06F13/16

Abstract: A memory system includes a memory controller and a memory. The memory controller selectively operates in a first mode and a second mode. In the first mode, the memory controller transmits a first command continuously during a plurality of clock cycles. In the second mode, the memory controller to mix a second command with the first command and transmit the mixture of the first command and the second command. The memory changes command latch timing depending on the first or second mode.

公开(公告)号：US20190065050A1

公开(公告)日：2019-02-28

申请号：US16169178

申请日：2018-10-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung-Jun SHIN ,  Tae-Young OH

IPC: G06F3/06 ,  G11C11/4076 ,  G11C7/10 ,  G06F13/16 ,  G11C8/10 ,  G11C8/18 ,  G11C7/22 ,  G11C8/06

CPC classification number: G06F3/06 ,  G06F13/1689 ,  G11C7/10 ,  G11C7/1045 ,  G11C7/1057 ,  G11C7/22 ,  G11C8/06 ,  G11C8/10 ,  G11C8/18 ,  G11C11/4076

Abstract: A memory system includes a memory controller and a memory. The memory controller selectively operates in a first mode and a second mode. In the first mode, the memory controller transmits a first command continuously during a plurality of clock cycles. In the second mode, the memory controller to mix a second command with the first command and transmit the mixture of the first command and the second command. The memory changes command latch timing depending on the first or second mode.

公开(公告)号：US20160196863A1

公开(公告)日：2016-07-07

申请号：US14970739

申请日：2015-12-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung-Jun SHIN ,  Sung-Min YIM

IPC: G11C11/406

CPC classification number: G11C11/406 ,  G11C7/02 ,  G11C11/40611 ,  G11C11/40618 ,  G11C11/40622 ,  G11C11/4087 ,  G11C29/783

Abstract: A method of operating a memory device comprises receiving a first row address corresponding to a first word line in the first sub bank array and corresponding to a first word line in the second sub bank array, determining whether at least one of the first word lines has been replaced with a spare word line, (a) when neither of the first word lines has been replaced, receiving a first number of row addresses for refresh operations in order to refresh adjacent word lines to the first word lines, and (b) when at least one of the first word lines has been replaced with a spare word line, receiving a second number of row addresses for refresh operations in order to refresh adjacent word lines to any non-replaced first word and any spare word lines, wherein the second number is greater than the first number.

Abstract translation: 一种操作存储器件的方法包括：接收对应于第一子存储体阵列中的第一字线的第一行地址并对应于第二子存储体阵列中的第一字线，确定第一字线中的至少一个是否具有 被替换为备用字线，（a）当两个第一字线都没有被替换时，接收刷新操作的第一数量的行地址以便刷新与第一字线相邻的字线，以及（b）当 第一字线中的至少一个已被替换为备用字线，接收用于刷新操作的第二数量的行地址，以便将相邻字线刷新到任何未替换的第一字和任何备用字线，其中第二字线 数字大于第一个数字。