公开(公告)号：US20200219898A1

公开(公告)日：2020-07-09

申请号：US16819907

申请日：2020-03-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kohji KANAMORI ,  Min-Yeong SONG ,  Shin-Hwan KANG

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/06

Abstract: A vertical memory device includes a lower circuit pattern on a substrate, a plurality of gate electrodes spaced apart from another in a first direction substantially perpendicular to an upper surface of the substrate on the lower circuit pattern, a channel extending through the gate electrodes in the first direction, a memory cell block including a first common source line (CSL) extending in a second direction substantially parallel to the upper surface of the substrate, and a first contact plug connected to the lower circuit pattern and the first CSL and overlapping the first CSL in the first direction.

公开(公告)号：US20230292515A1

公开(公告)日：2023-09-14

申请号：US18321080

申请日：2023-05-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-Hwan SON ,  Kohji KANAMORI ,  Shin-Hwan KANG ,  Young Jin KWON

IPC: H10B43/27 ,  H01L23/535 ,  H10B43/40

CPC classification number: H10B43/27 ,  H01L23/535 ,  H10B43/40

Abstract: A vertical memory device includes gate electrodes on a substrate, a channel extending through the gate electrodes, and a contact plug extending through the gate electrodes. The gate electrodes are stacked in a first direction substantially vertical to an upper surface of the substrate and arranged to have a staircase shape including steps of which extension lengths in a second direction substantially parallel to the upper surface gradually increase from a lowermost level toward an uppermost level. A pad at an end portion of each of the gate electrodes in the second direction has a thickness greater than those of other portions thereof. The channel extends in the first direction. The contact plug extends in the first direction. The channel contacts the pad of a first gate electrode among the gate electrodes to be electrically connected thereto, and is electrically insulated from second gate electrodes among the gate electrodes.

公开(公告)号：US20200043943A1

公开(公告)日：2020-02-06

申请号：US16354448

申请日：2019-03-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Shin-Hwan KANG ,  SUN-IL SHIM ,  SEUNG HYUN

IPC: H01L27/11582 ,  H01L29/423 ,  H01L23/535 ,  H01L27/11573 ,  H01L29/45

Abstract: A vertical memory device includes first gate electrodes stacked on a cell region of a substrate and spaced apart from each other in a vertical direction substantially perpendicular to an upper surface of the substrate, a channel extending through the first gate electrodes and extending in the vertical direction, a first contact plug structure contacting a corresponding one of the first gate electrodes, extending in the vertical direction, and including a first metal pattern, a first barrier pattern covering a lower surface and a sidewall of the first metal pattern and a first metal silicide pattern covering a lower surface and a sidewall of the first barrier pattern, and a second contact plug structure extending in the vertical direction on a peripheral circuit region of the substrate and including a second metal pattern and a second barrier pattern covering a lower surface and a sidewall of the second metal pattern.

公开(公告)号：US20190013330A1

公开(公告)日：2019-01-10

申请号：US16117036

申请日：2018-08-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kohji KANAMORI ,  Shin-Hwan KANG ,  Young-Woo PARK ,  Jung-Hoon PARK

IPC: H01L27/11582 ,  H01L49/02 ,  H01L29/423

CPC classification number: H01L27/11582 ,  H01L28/00 ,  H01L29/42344

Abstract: A vertical memory device includes insulating interlayer patterns, of gate electrodes, a channel, and a charge storage pattern structure. The insulating interlayer patterns are spaced in a first direction. The gate electrodes between are neighboring insulating interlayer patterns, respectively. The channel extends through the insulating interlayer patterns and the gate electrodes in the first direction. The charge storage pattern structure includes a tunnel insulation pattern, a charge trapping pattern structure, and a blocking pattern sequentially stacked between the channel and each of the gate electrodes in a second direction. The charge trapping pattern structure includes charge trapping patterns spaced in the first direction. The charge trapping patterns are adjacent to sidewalls of first gate electrodes, respectively. A first charge trapping pattern extends in the first direction along a sidewall of a first insulating interlayer pattern.

公开(公告)号：US20220254808A1

公开(公告)日：2022-08-11

申请号：US17728759

申请日：2022-04-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kohji KANAMORI ,  Min-Yeong SONG ,  Shin-Hwan KANG

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/06

Abstract: A vertical memory device includes a lower circuit pattern on a substrate, a plurality of gate electrodes spaced apart from another in a first direction substantially perpendicular to an upper surface of the substrate on the lower circuit pattern, a channel extending through the gate electrodes in the first direction, a memory cell block including a first common source line (CSL) extending in a second direction substantially parallel to the upper surface of the substrate, and a first contact plug connected to the lower circuit pattern and the first CSL and overlapping the first CSL in the first direction.

公开(公告)号：US20220028740A1

公开(公告)日：2022-01-27

申请号：US17450726

申请日：2021-10-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Shin-Hwan KANG ,  SUN-IL SHIM ,  SEUNG HYUN

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/535 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582 ,  H01L27/11573

Abstract: A vertical memory device includes first gate electrodes stacked on a cell region of a substrate and spaced apart from each other in a vertical direction substantially perpendicular to an upper surface of the substrate, a channel extending through the first gate electrodes and extending in the vertical direction, a first contact plug structure contacting a corresponding one of the first gate electrodes, extending in the vertical direction, and including a first metal pattern, a first barrier pattern covering a lower surface and a sidewall of the first metal pattern and a first metal silicide pattern covering a lower surface and a sidewall of the first barrier pattern, and a second contact plug structure extending in the vertical direction on a peripheral circuit region of the substrate and including a second metal pattern and a second barrier pattern covering a lower surface and a sidewall of the second metal pattern.