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公开(公告)号：US10547000B2
公开(公告)日：2020-01-28
申请号：US16014871
申请日：2018-06-21
Applicant: Samsung Electronics Co., Ltd.
Inventor： Ji-Hyun Jeong , Ilmok Park , Si-Ho Song
Abstract: Disclosed are a variable resistance memory device and a method of manufacturing the same. The device comprises a first conductive line extending in a first direction, a second conductive line extending in a second direction intersecting the first direction, a memory cell at an intersection between the first conductive line and the second conductive line, a first electrode between the first conductive line and the memory cell, and a second electrode between the second conductive line and the memory cell. The memory cell comprises a switching pattern, an intermediate electrode, a first resistivity control pattern, and a variable resistance pattern that are connected in series between the first conductive line and the second conductive line. Resistivity of the first resistivity control pattern is less than resistivity of the second electrode.
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Patent Agency Ranking
公开(公告)号：US11665914B2
公开(公告)日：2023-05-30
申请号：US17406166
申请日：2021-08-19
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Si-Ho Song , Jeonghee Park , Changhyun Cho
CPC classification number: H01L27/249 , G11C5/063 , H01L45/06 , H01L45/1253 , H01L45/141
Abstract: A three-dimensional semiconductor memory device includes first conductive lines extending horizontally in a first direction, a second conductive line extending vertically in a second direction perpendicular to the first direction, and memory cells at cross-points between the first conductive lines and the second conductive line. The first conductive lines are laterally spaced apart from each other in a third direction crossing the first direction. Each of the memory cells includes a variable resistance element and a switching element that are horizontally arranged. The variable resistance element includes a first variable resistance pattern and a second variable resistance pattern arranged in the second direction, a first electrode between the first variable resistance pattern and the first conductive line, a second electrode between the second variable resistance pattern and the second conductive line, and a third electrode between the first variable resistance pattern and the second variable resistance pattern.
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公开(公告)号：US20150049999A1
公开(公告)日：2015-02-19
申请号：US14359524
申请日：2012-11-22
Applicant: Samsung Electronics Co., Ltd. , Industry-Academic Cooperation Foundation, Yonsei University
Inventor： Yeong-Seop Lee , Mun-Hyun Do , Si-Ho Song , Dea-Hwan Oh , Dae-Seung Moon , Kyung-Hwan Oh
CPC classification number: G02B6/0281 , B29K2995/0031 , G02B6/036 , G02B6/03611 , G02B6/03661
Abstract: An ultra-low loss optical fiber is provided. The ultra-low loss optical fiber includes a core having the maximum refractive index inside an optical fiber, and placed at the central portion of the optical fiber, a trench having the minimum refractive index inside the optical fiber and encompassing the core, and a cladding encompassing the trench. The core includes a first sub-core layer having the maximum refractive index inside the optical fiber, and placed at the center of the optical fiber, a second sub-core layer having a refractive index lower than that of the first sub-core layer and encompassing the first sub-core layer, and a third sub-core layer having a refractive index lower than that of the second sub-core layer and encompassing the second sub-core layer.
Abstract translation: 提供超低损耗光纤。 超低损耗光纤包括在光纤内部具有最大折射率的芯，并且放置在光纤的中心部分处，在光纤内具有最小折射率并且包围芯的沟槽和包层 包围沟槽。 芯包括在光纤内具有最大折射率的第一子芯层，并且放置在光纤的中心，具有折射率低于第一子芯层的折射率的第二子芯层和 包括第一子芯层和折射率低于第二子芯层的折射率并包围第二子芯层的第三子芯层。
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公开(公告)号：US11127792B2
公开(公告)日：2021-09-21
申请号：US16710450
申请日：2019-12-11
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Si-Ho Song , Jeonghee Park , Changhyun Cho
Abstract: A three-dimensional semiconductor memory device includes first conductive lines extending horizontally in a first direction, a second conductive line extending vertically in a second direction perpendicular to the first direction, and memory cells at cross-points between the first conductive lines and the second conductive line. The first conductive lines are laterally spaced apart from each other in a third direction crossing the first direction. Each of the memory cells includes a variable resistance element and a switching element that are horizontally arranged. The variable resistance element includes a first variable resistance pattern and a second variable resistance pattern arranged in the second direction, a first electrode between the first variable resistance pattern and the first conductive line, a second electrode between the second variable resistance pattern and the second conductive line, and a third electrode between the first variable resistance pattern and the second variable resistance pattern.
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公开(公告)号：US10985213B2
公开(公告)日：2021-04-20
申请号：US16780014
申请日：2020-02-03
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Si-Ho Song , Youngbae Kim , Dueung Kim , Changhyun Cho
Abstract: A nonvolatile memory device includes a memory cell array, a word line drive block that is connected to a first group of memory cells through a first group of word lines and to a second group of memory cells through a second group of word lines, a bit line bias and sense block that is connected to the first and second groups of memory cells through bit lines, a variable current supply block that generates a word line current to be supplied to a selected word line, and a control logic block that receives an address and a command and controls the variable current supply block to adjust an amount of the word line current based on the address. The control logic block further varies the amount of the word line current depending on a distance between the selected word line and the substrate.
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公开(公告)号：US10923655B2
公开(公告)日：2021-02-16
申请号：US16726513
申请日：2019-12-24
Applicant: Samsung Electronics Co., Ltd.
Inventor： Ji-Hyun Jeong , Ilmok Park , Si-Ho Song
Abstract: Disclosed are a variable resistance memory device and a method of manufacturing the same. The device comprises a first conductive line extending in a first direction, a second conductive line extending in a second direction intersecting the first direction, a memory cell at an intersection between the first conductive line and the second conductive line, a first electrode between the first conductive line and the memory cell, and a second electrode between the second conductive line and the memory cell. The memory cell comprises a switching pattern, an intermediate electrode, a first resistivity control pattern, and a variable resistance pattern that are connected in series between the first conductive line and the second conductive line. Resistivity of the first resistivity control pattern is less than resistivity of the second electrode.
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