公开(公告)号：US20190355671A1

公开(公告)日：2019-11-21

申请号：US16530993

申请日：2019-08-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yun-Rae CHO ,  Sundae KIM ,  HYUNGGIL BAEK ,  Namgyu BAEK ,  Seunghun SHIN ,  Donghoon WON

IPC: H01L23/00 ,  H01L21/78 ,  H01L23/58 ,  H01L21/02

Abstract: A method of dividing a substrate includes preparing a substrate including a crystalline semiconductor layer having a scribe lane region and device regions, a dielectric layer on the crystalline semiconductor layer, and a partition structure in physical contact with the dielectric layer and provided on the scribe lane region of the crystalline semiconductor layer, forming an amorphous region in the crystalline semiconductor layer, and performing a grinding process on the crystalline semiconductor layer after the forming of the amorphous region. The amorphous region is formed in the scribe lane region of the crystalline semiconductor layer.

公开(公告)号：US20180261555A1

公开(公告)日：2018-09-13

申请号：US15850336

申请日：2017-12-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yun-Rae CHO ,  Sundae KIM ,  Hyunggil Baek ,  Namgyu BAEK ,  Seunghun SHIN ,  Donghoon WON

IPC: H01L23/00 ,  H01L21/78 ,  H01L21/02

Abstract: A method of dividing a substrate includes preparing a substrate including a crystalline semiconductor layer having a scribe lane region and device regions, a dielectric layer on the crystalline semiconductor layer, and a partition structure in physical contact with the dielectric layer and provided on the scribe lane region of the crystalline semiconductor layer, forming an amorphous region in the crystalline semiconductor layer, and performing a grinding process on the crystalline semiconductor layer after the forming of the amorphous region. The amorphous region is formed in the scribe lane region of the crystalline semiconductor layer.

公开(公告)号：US20170294360A1

公开(公告)日：2017-10-12

申请号：US15630934

申请日：2017-06-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sundae KIM ,  Yun-Rae CHO ,  Namgyu BAEK ,  Seokhyun LEE

IPC: H01L21/66 ,  H01L21/768

CPC classification number: H01L22/32 ,  H01L21/76877 ,  H01L21/822 ,  H01L22/14 ,  H01L22/34 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/10897

Abstract: Provided is a semiconductor device including an interconnection structure provided on a cell region of a substrate to include a first line and a second line sequentially stacked on the substrate, and a defect detection structure provided on a peripheral region of the substrate to include first and second defect detection lines provided at the same levels as those of the first and second lines, respectively.

公开(公告)号：US20160233171A1

公开(公告)日：2016-08-11

申请号：US14985379

申请日：2015-12-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sundae KIM ,  Yun-Rae CHO ,  Namgyu BAEK ,  Seokhyun LEE

IPC: H01L23/544

CPC classification number: H01L22/32 ,  H01L21/76877 ,  H01L21/822 ,  H01L22/14 ,  H01L22/34 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/10897

Abstract: Provided is a semiconductor device including an interconnection structure provided on a cell region of a substrate to include a first line and a second line sequentially stacked on the substrate, and a defect detection structure provided on a peripheral region of the substrate to include first and second defect detection lines provided at the same levels as those of the first and second lines, respectively.

Abstract translation: 本发明提供一种半导体器件，其包括设置在基板的单元区域上的互连结构，包括依次层叠在基板上的第一线和第二线，以及设置在基板的周边区域上的缺陷检测结构，包括第一和第二 缺陷检测线分别与第一和第二线的级别相同。