公开(公告)号：US20230187285A1

公开(公告)日：2023-06-15

申请号：US17883250

申请日：2022-08-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： SANG-WON LEE ,  HYUNKI KIM ,  YOUNG-JA KIM ,  HYUNGGIL BAEK

IPC: H01L21/66 ,  H01L23/00

CPC classification number: H01L22/12 ,  H01L24/75 ,  H01L24/81 ,  H01L2224/75621 ,  H01L2224/75001 ,  H01L2224/81194 ,  H01L2224/8118

Abstract: A method of manufacturing a semiconductor package includes estimating an error in a solder ball attaching process, determining a specification of a ball tool and a method of the solder ball attaching process, based on the estimated error, manufacturing the ball tool according to the determined specification thereof, and performing the solder ball attaching process based on the method of the solder ball attaching process. The determining of the specification of the ball tool and the method of the solder ball attaching process includes determining a number of a plurality of holders in the ball tool and a position and a width of each of the plurality of holders, determining a number of a plurality of working regions of a substrate and a position and a width of each of the plurality of working regions, and dividing a substrate into the plurality of working regions.

公开(公告)号：US20240421011A1

公开(公告)日：2024-12-19

申请号：US18435689

申请日：2024-02-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： WanSun Kim ,  HYUNGGIL BAEK ,  Hojin Seo

IPC: H01L23/18 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065 ,  H01L25/18

Abstract: A semiconductor package includes a package substrate, a semiconductor chip that is bonded to the package substrate, and a stiffener that is adjacent to the semiconductor chip and is bonded to the package substrate. The stiffener includes a plurality of corner parts that are bonded to a plurality of corner regions of the package substrate, and a plurality of leg parts that are spaced apart from the package substrate. Each of the plurality of leg parts connects corresponding two leg parts of the plurality of leg parts with each other.

公开(公告)号：US20240203958A1

公开(公告)日：2024-06-20

申请号：US18352177

申请日：2023-07-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SHLE-GE LEE ,  HYUNGGIL BAEK ,  GYUNGHWAN OH

IPC: H01L25/10 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065 ,  H10B80/00

CPC classification number: H01L25/105 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/16 ,  H01L25/0652 ,  H01L28/40 ,  H10B80/00 ,  H01L2224/16225

Abstract: A semiconductor package includes a lower substrate that has a contact region and a non-contact region, a first upper substrate on the lower substrate, a lower device on the first upper substrate, a plurality of first solder balls between the first upper substrate and the lower substrate contact region, a plurality of capacitors between the first upper substrate and the lower substrate non-contact region, and a plurality of support blocks between the plurality of capacitors and the lower substrate non-contact region.

公开(公告)号：US20190355671A1

公开(公告)日：2019-11-21

申请号：US16530993

申请日：2019-08-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yun-Rae CHO ,  Sundae KIM ,  HYUNGGIL BAEK ,  Namgyu BAEK ,  Seunghun SHIN ,  Donghoon WON

IPC: H01L23/00 ,  H01L21/78 ,  H01L23/58 ,  H01L21/02

Abstract: A method of dividing a substrate includes preparing a substrate including a crystalline semiconductor layer having a scribe lane region and device regions, a dielectric layer on the crystalline semiconductor layer, and a partition structure in physical contact with the dielectric layer and provided on the scribe lane region of the crystalline semiconductor layer, forming an amorphous region in the crystalline semiconductor layer, and performing a grinding process on the crystalline semiconductor layer after the forming of the amorphous region. The amorphous region is formed in the scribe lane region of the crystalline semiconductor layer.