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公开(公告)号:US11095876B2
公开(公告)日:2021-08-17
申请号:US16252806
申请日:2019-01-21
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Sung Ho Jun , Chang Soo Park , Moon Kyu Song , Kyung Koo Lee , Kil Whan Lee , Hyuk Jae Jang , Kyung Ah Jeong
IPC: H04N19/103 , H04N19/46 , H04N19/91 , G06F13/16 , H04N19/186 , H04N19/176 , H04N19/124 , H04N19/12
Abstract: Provided is an image processing device configured to compress first image data. The image processing device includes an encoding circuit configured to compress the first image data into second image data including prediction data and residual data, compress the second image data into third image data by performing entropy encoding on the second image data, generate a header representing a compression ratio of the third image data, and store the third image data along with the header in a memory device as compressed first image data.
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公开(公告)号:US11726949B2
公开(公告)日:2023-08-15
申请号:US17570863
申请日:2022-01-07
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Jung Yeop Yang , Ju Won Byun , Sung Ho Jun , Yo Won Jeong
IPC: G06F15/78
CPC classification number: G06F15/7821
Abstract: Provided are a stream reprocessing system on chip (SoC) and a method for operating the same is provided. The stream reprocessing system includes a plurality of processors including a central processing unit (CPU); a memory controller configured to receive a stream; and a stream reprocessor configured to perform reprocessing the stream, wherein the stream reprocessor includes: a control unit configured to determine whether to perform the reprocessing on the stream; a reprocessing unit configured to reprocess the stream based on receiving a command to perform the reprocessing on the stream from the control unit; and an output unit configured to transmit the reprocessed stream to a memory.
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公开(公告)号:US11044466B2
公开(公告)日:2021-06-22
申请号:US16252796
申请日:2019-01-21
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Sung Ho Jun , Yo-Han Lim
IPC: H04N19/103 , H04N19/91 , H04N19/182 , H04N19/124
Abstract: An image processing device for performing a data decompression is provided. The image processing device includes a decoder circuit having a plurality of stages for decompressing compressed image data of a plurality of pixels. The decoder circuit is configured to divide the pixels into a plurality of groups. The first stage performs prediction compensation on the compressed image data of a first pixel of the first group at a first time to generate first prediction data, and performs the prediction compensation on the compressed image data of a second pixel of the first group at a second time using the first prediction data. The second stage performs the prediction compensation on the compressed image data of a first pixel of the second group at the second time using the first prediction data, to generate second prediction data.
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公开(公告)号:US10887616B2
公开(公告)日:2021-01-05
申请号:US16521147
申请日:2019-07-24
Applicant: Samsung Electronics Co., Ltd.
Inventor: Sung Ho Jun , Sung Ho Roh , Hyuk Jae Jang
IPC: H04N5/92 , H04N19/46 , H04N19/13 , H04N19/50 , H04N19/70 , H04N19/103 , H04N19/146 , H04N19/124 , H04N5/917
Abstract: An image processing device includes a frame buffer compressor, which is configured to: (i) compress source data into compressed data having CRC bits appended thereto, and (ii) decompress the compressed data into output data and use the CRC bits to check for errors in the output data. A multimedia device is provided, which is configured to generate the source data in response to raw data. A memory device is provided, which is configured to store the compressed data. The frame buffer compressor may include an encoder configured to compress the source data into the compressed data with the CRC bits appended thereto, and a decoder configured to decompress the compressed data into the output data. The encoder may include a prediction module, which is configured to generate prediction data including reference data and residual data, from the source data.
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公开(公告)号:US10362315B2
公开(公告)日:2019-07-23
申请号:US14830188
申请日:2015-08-19
Applicant: Samsung Electronics Co., Ltd.
Inventor: Sung Ho Jun , Nyeong Kyu Kwon
IPC: H04B1/66 , H04N7/12 , H04N11/02 , H04N11/04 , H04N19/167 , H04N19/124 , H04N19/14 , H04N19/172 , H04N19/142 , H04N19/17 , H04N19/20
Abstract: A method, codec device, and system on chip (SoC) are provided for coding a region of interest (ROI) object of a frame. A current frame, which includes the ROI object is received, and a type of the current frame is determined. A complexity of the current frame is estimated. An ROI control signal is generated for controlling ROI coding of the ROI object based on the complexity.
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公开(公告)号:US20190069033A1
公开(公告)日:2019-02-28
申请号:US15866959
申请日:2018-01-10
Applicant: Samsung Electronics Co., Ltd.
Inventor: Sung Ho Jun , Yo Won Jeong
IPC: H04N21/4728 , H04N19/10 , H04N7/01 , G06T3/40
Abstract: A video encoding apparatus may include a memory storing interest region information for each of a plurality of scenarios and a neural processing unit (NPU) extracting interest region information corresponding to a scenario of an input video from the memory or updating the interest region information stored in the memory based on an user input.
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公开(公告)号:US11677932B2
公开(公告)日:2023-06-13
申请号:US17243657
申请日:2021-04-29
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Sung Ho Jun , Yo-Han Lim
IPC: H04N19/103 , H04N19/91 , H04N19/182 , H04N19/124
CPC classification number: H04N19/103 , H04N19/124 , H04N19/182 , H04N19/91
Abstract: An image processing device for performing a data decompression is provided. The image processing device includes a decoder circuit having a plurality of stages for decompressing compressed image data of a plurality of pixels. The decoder circuit is configured to divide the pixels into a plurality of groups. The first stage performs prediction compensation on the compressed image data of a first pixel of the first group at a first time to generate first prediction data, and performs the prediction compensation on the compressed image data of a second pixel of the first group at a second time using the first prediction data. The second stage performs the prediction compensation on the compressed image data of a first pixel of the second group at the second time using the first prediction data, to generate second prediction data.
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公开(公告)号:US11445160B2
公开(公告)日:2022-09-13
申请号:US17034403
申请日:2020-09-28
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Sung Ho Jun , Kil Whan Lee
IPC: H04N9/808 , G11B20/00 , H04N9/825 , G11B20/10 , H04N19/186 , H04N19/00 , H04N19/176 , H04N19/61 , H04N19/124 , H04N19/146 , H04N19/60 , H04N19/91 , H04N19/50
Abstract: An image processing device includes a multimedia intellectual property (IP) block which processes image data including a first component and a second component; a memory; and a frame buffer compressor (FBC) which compresses the image data to generate compressed data and stores the compressed data in the memory. The frame buffer compressor includes a logic circuit which controls a compression sequence of the first component and the second component of the image data.
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公开(公告)号:US11019337B2
公开(公告)日:2021-05-25
申请号:US15903278
申请日:2018-02-23
Applicant: Samsung Electronics Co., Ltd.
Inventor: Sung Ho Jun , Jung Yeop Yang
IPC: H04N19/124 , H04N19/61 , H04N19/176 , H04N19/115 , H04N19/167 , H04N19/174 , H04N19/152 , H04N19/12 , H04N19/184 , H04N19/63
Abstract: A video encoding apparatus may include a partitioning unit which divides a frame included in input video into a plurality of blocks and a rate control module which adjusts a first quantization parameter value of a block corresponding to a region of interest among the plurality of blocks based on a first CBF (current buffer fullness) value of the region of interest, and adjusts a second quantization parameter value of a block corresponding to a non-region of interest among the plurality of blocks based on a second CBF value of the non-region of interest.
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公开(公告)号:US10819965B2
公开(公告)日:2020-10-27
申请号:US16181957
申请日:2018-11-06
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Sung Ho Jun , Kil Whan Lee
IPC: H04N9/80 , H04N9/808 , G11B20/00 , H04N9/825 , G11B20/10 , H04N19/186 , H04N19/00 , H04N19/176 , H04N19/61 , H04N19/124 , H04N19/146 , H04N19/60 , H04N19/91 , H04N19/50
Abstract: An image processing device includes a multimedia intellectual property (IP) block which processes image data including a first component and a second component; a memory; and a frame buffer compressor (FBC) which compresses the image data to generate compressed data and stores the compressed data in the memory. The frame buffer compressor includes a logic circuit which controls a compression sequence of the first component and the second component of the image data.
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