公开(公告)号：US20140133872A1

公开(公告)日：2014-05-15

申请号：US13721208

申请日：2012-12-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung Woo KANG ,  Jin Gue Ko ,  Hyun Joon Keum ,  Seung Jun Lee

IPC: G03G15/20

CPC classification number: G03G15/2028 ,  G03G15/2064

Abstract: A fixing unit which may be disposed in an image forming includes a heating roller, at least one pressure roller being in pressure contact with the heating roller to form a nip together with the heating roller, and a pressure releasing member partially restricting application of pressure to the nip. The nip includes an effective fixing section used for fixing. The pressure releasing member includes a pair of pressure releasing parts inserted into sections of the nip other than the effective fixing section, a connection part connecting the pair of pressure releasing parts, and guide parts extending from the connection part in the same direction as the pair of pressure releasing parts. The pressure releasing member prevents deformation of a portion of an elastic layer formed on the heating roller which corresponds to the effective fixing section.

Abstract translation: 可以设置在图像形成中的定影单元包括加热辊，至少一个加压辊与加热辊压力接触以与加热辊一起形成辊隙，并且压力释放构件部分地限制施加压力 nip 辊隙包括用于固定的有效固定部分。 压力释放构件包括插入除了有效固定部分之外的辊隙部分中的一对压力释放部件，连接一对压力释放部件的连接部件和从连接部件沿与该对部件相同的方向延伸的引导部件 的压力释放部件。 压力释放构件防止形成在与有效固定部分相对应的加热辊上的弹性层的一部分的变形。

公开(公告)号：US20190295889A1

公开(公告)日：2019-09-26

申请号：US16176943

申请日：2018-10-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keun Hee BAI ,  Sung Woo KANG ,  Kee Sang KWON ,  Dong Seok LEE ,  Sang Hyun LEE ,  Jeong Yun LEE ,  Yong-Ho JEON

IPC: H01L21/768 ,  H01L21/8234 ,  H01L29/51 ,  H01L29/66

Abstract: A semiconductor device with improved product reliability and a method of fabricating the semiconductor are provided. The semiconductor device includes a substrate, a gate electrode on the substrate, a first spacer on a sidewall of the gate electrode, a conductive contact on a sidewall of the first spacer to protrude beyond a top surface of the gate electrode, a trench defined by the top surface of the gate electrode, a top surface of the first spacer, and sidewalls of the contact, an etching stop layer extending along at least parts of sidewalls of the trench and a bottom surface of the trench, and a capping pattern on the etching stop layer to fill the trench, wherein the capping pattern includes silicon oxide or a low-k material having a lower permittivity than silicon oxide.

公开(公告)号：US20230231024A1

公开(公告)日：2023-07-20

申请号：US17982634

申请日：2022-11-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hong Sik SHIN ,  Jeong Yeon SEO ,  Sung Woo KANG ,  Dong Kwon KIM

IPC: H01L29/417 ,  H01L29/78

CPC classification number: H01L29/41791 ,  H01L29/7851

Abstract: The semiconductor device including an active pattern on a substrate and extending in a first direction, a gate structure on the active pattern, including a gate electrode extending in a second direction different from the first direction, a source/drain pattern on at least one side of the gate structure, and a source/drain contact on the source/drain pattern and connected to the source/drain pattern, wherein with respect to an upper surface of the active pattern, a height of an upper surface of the gate electrode is same as a height of an upper surface of the source/drain contact, and the source/drain contact comprises a lower source/drain contact and an upper source/drain contact on the lower source/drain contact, may be provided.

公开(公告)号：US20230058116A1

公开(公告)日：2023-02-23

申请号：US17659135

申请日：2022-04-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HONG SIK SHIN ,  Sung Woo KANG ,  Dong Kwon KIM

IPC: H01L29/417

Abstract: A semiconductor device includes a substrate, an active pattern disposed on the substrate and that extends in a first horizontal direction, a field insulating layer disposed on the substrate and that surrounds a sidewall of the active pattern, a gate electrode disposed on the field insulating layer and that extends in a second horizontal direction, a source/drain region disposed on a side of the gate electrode, a first interlayer insulating layer disposed on the field insulating layer and that surrounds a portion of a sidewall of the source/drain region, a second interlayer insulating layer disposed on the first interlayer insulating layer and that surrounds a sidewall of the gate electrode, and a source/drain contact that penetrates through the second interlayer insulating layer and is electrically connected to the source/drain region. The source/drain contact includes a skirt that protrudes from a lower sidewall toward the second interlayer insulating.