公开(公告)号：US11004976B2

公开(公告)日：2021-05-11

申请号：US16351328

申请日：2019-03-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungkwan Kang ,  Keum Seok Park ,  Byeongchan Lee ,  Sangbom Kang ,  Nam-Kyu Kim

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/49 ,  H01L29/51 ,  H01L21/335

Abstract: A semiconductor device has a silicide source/drain region is fabricated by growing silicon on an epitaxial region including silicon and either germanium or carbon. In the method, a gate electrode is formed on a semiconductor substrate with a gate insulating layer interposed therebetween. An epitaxial layer is formed in the semiconductor substrate at both sides of the gate electrodes. A silicon layer is formed to cap the epitaxial layer. The silicon layer and a metal material are reacted to form a silicide layer. In a PMOS, the epitaxial layer has a top surface and inclined side surfaces that are exposed above the upper surface of the active region. The silicon layer is grown on the epitaxial layer in such a way as to cap the top and inclined surfaces.

公开(公告)号：US10263109B2

公开(公告)日：2019-04-16

申请号：US14995215

申请日：2016-01-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungkwan Kang ,  Keum Seok Park ,  Byeongchan Lee ,  Sangbom Kang ,  Nam-Kyu Kim

IPC: H01L21/8234 ,  H01L21/44 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/49 ,  H01L29/51

Abstract: A semiconductor device has a silicide source/drain region is fabricated by growing silicon on an epitaxial region including silicon and either germanium or carbon. In the method, a gate electrode is formed on a semiconductor substrate with a gate insulating layer interposed therebetween. An epitaxial layer is formed in the semiconductor substrate at both sides of the gate electrodes. A silicon layer is formed to cap the epitaxial layer. The silicon layer and a metal material are reacted to form a silicide layer. In a PMOS, the epitaxial layer has a top surface and inclined side surfaces that are exposed above the upper surface of the active region. The silicon layer is grown on the epitaxial layer in such a way as to cap the top and inclined surfaces.

公开(公告)号：US20190214498A1

公开(公告)日：2019-07-11

申请号：US16351328

申请日：2019-03-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungkwan Kang ,  Keum Seok Park ,  Byeongchan Lee ,  Sangbom Kang ,  Nam-Kyu Kim

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L29/49 ,  H01L29/51 ,  H01L29/08 ,  H01L21/8238

CPC classification number: H01L29/7848 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/0847 ,  H01L29/4975 ,  H01L29/51 ,  H01L29/518 ,  H01L29/665 ,  H01L29/66507 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636

Abstract: A semiconductor device has a silicide source/drain region is fabricated by growing silicon on an epitaxial region including silicon and either germanium or carbon. In the method, a gate electrode is formed on a semiconductor substrate with a gate insulating layer interposed therebetween. An epitaxial layer is formed in the semiconductor substrate at both sides of the gate electrodes. A silicon layer is formed to cap the epitaxial layer. The silicon layer and a metal material are reacted to form a silicide layer. In a PMOS, the epitaxial layer has a top surface and inclined side surfaces that are exposed above the upper surface of the active region. The silicon layer is grown on the epitaxial layer in such a way as to cap the top and inclined surfaces.

公开(公告)号：US20150031183A1

公开(公告)日：2015-01-29

申请号：US14485035

申请日：2014-09-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungkwan Kang ,  Keum Seok Park ,  Byeongchan Lee ,  Sangbom Kang ,  Nam-Kyu Kim

IPC: H01L29/66

CPC classification number: H01L29/7848 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/0847 ,  H01L29/4975 ,  H01L29/51 ,  H01L29/518 ,  H01L29/665 ,  H01L29/66507 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636

Abstract: A semiconductor device has a silicide source/drain region is fabricated by growing silicon on an epitaxial region including silicon and either germanium or carbon. In the method, a gate electrode is formed on a semiconductor substrate with a gate insulating layer interposed therebetween. An epitaxial layer is formed in the semiconductor substrate at both sides of the gate electrodes. A silicon layer is formed to cap the epitaxial layer. The silicon layer and a metal material are reacted to form a silicide layer. In a PMOS, the epitaxial layer has a top surface and inclined side surfaces that are exposed above the upper surface of the active region. The silicon layer is grown on the epitaxial layer in such a way as to cap the top and inclined surfaces.

Abstract translation: 通过在包括硅和锗或锗的外延区域上生长硅来制造具有硅化物源极/漏极区的半导体器件。 在该方法中，在半导体衬底上形成有栅极绝缘层的栅电极。 在栅极两侧的半导体衬底中形成外延层。 形成硅层来覆盖外延层。 硅层和金属材料反应形成硅化物层。 在PMOS中，外延层具有暴露在有源区的上表面上方的顶表面和倾斜侧表面。 硅层在外延层上生长，以覆盖顶部和倾斜表面。

公开(公告)号：US10170622B2

公开(公告)日：2019-01-01

申请号：US15619882

申请日：2017-06-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungkwan Kang ,  Keum Seok Park ,  Byeongchan Lee ,  Sangbom Kang ,  Nam-Kyu Kim

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/49 ,  H01L29/51 ,  H01L21/335

Abstract: A semiconductor device has a silicide source/drain region is fabricated by growing silicon on an epitaxial region including silicon and either germanium or carbon. In the method, a gate electrode is formed on a semiconductor substrate with a gate insulating layer interposed therebetween. An epitaxial layer is formed in the semiconductor substrate at both sides of the gate electrodes. A silicon layer is formed to cap the epitaxial layer. The silicon layer and a metal material are reacted to form a silicide layer. In a PMOS, the epitaxial layer has a top surface and inclined side surfaces that are exposed above the upper surface of the active region. The silicon layer is grown on the epitaxial layer in such a way as to cap the top and inclined surfaces.

公开(公告)号：US20170278967A1

公开(公告)日：2017-09-28

申请号：US15619882

申请日：2017-06-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungkwan Kang ,  Keum Seok Park ,  Byeongchan Lee ,  Sangbom Kang ,  Nam-Kyu Kim

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/08 ,  H01L29/51 ,  H01L21/02

CPC classification number: H01L29/7848 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/0847 ,  H01L29/4975 ,  H01L29/51 ,  H01L29/518 ,  H01L29/665 ,  H01L29/66507 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636

Abstract: A semiconductor device has a silicide source/drain region is fabricated by growing silicon on an epitaxial region including silicon and either germanium or carbon. In the method, a gate electrode is formed on a semiconductor substrate with a gate insulating layer interposed therebetween. An epitaxial layer is formed in the semiconductor substrate at both sides of the gate electrodes. A silicon layer is formed to cap the epitaxial layer. The silicon layer and a metal material are reacted to form a silicide layer. In a PMOS, the epitaxial layer has a top surface and inclined side surfaces that are exposed above the upper surface of the active region. The silicon layer is grown on the epitaxial layer in such a way as to cap the top and inclined surfaces.

公开(公告)号：US20160133748A1

公开(公告)日：2016-05-12

申请号：US14995215

申请日：2016-01-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungkwan Kang ,  Keum Seok Park ,  Byeongchan Lee ,  Sangbom Kang ,  Nam-Kyu Kim

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/49 ,  H01L29/08 ,  H01L29/51 ,  H01L21/8238 ,  H01L21/02

CPC classification number: H01L29/7848 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/0847 ,  H01L29/4975 ,  H01L29/51 ,  H01L29/518 ,  H01L29/665 ,  H01L29/66507 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636

Abstract: A semiconductor device has a silicide source/drain region is fabricated by growing silicon on an epitaxial region including silicon and either germanium or carbon. In the method, a gate electrode is formed on a semiconductor substrate with a gate insulating layer interposed therebetween. An epitaxial layer is formed in the semiconductor substrate at both sides of the gate electrodes. A silicon layer is formed to cap the epitaxial layer. The silicon layer and a metal material are reacted to form a silicide layer. In a PMOS, the epitaxial layer has a top surface and inclined side surfaces that are exposed above the upper surface of the active region. The silicon layer is grown on the epitaxial layer in such a way as to cap the top and inclined surfaces.