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12 条记录 (耗时 0.024 秒)

    NEURAL PROCESSOR
    2.
    发明申请
    NEURAL PROCESSOR 有权

    公开(公告)号：US20220283984A1

    公开(公告)日：2022-09-08

    申请号：US17369298

    申请日：2021-07-07

    申请人： SAMSUNG ELECTRONICS CO., LTD. ,  SNU R&DB FOUNDATION

    发明人： Dongyoung KIM ,  Jung Ho AHN ,  Sunjung LEE ,  Jaewan CHOI

    IPC分类号： G06F15/80 ,  G06N3/063 ,  G06F9/30

    摘要： A neural processor is provided. The neural processor includes a matrix device which is configured to generate an output feature map by processing a standard convolution operation and which has a systolic array architecture, and accelerators with an adder-tree structure which are configured to process depth-wise convolution operations for each of elements of the output feature map corresponding to lanes of the matrix device.

    SEMICONDUCTOR DEVICE
    3.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20210104524A1

    公开(公告)日：2021-04-08

    申请号：US16898719

    申请日：2020-06-11

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Yoon Tae HWANG ,  Sunjung LEE ,  Heonbok LEE ,  Geunwoo KIM ,  Wandon KIM

    IPC分类号： H01L27/092 ,  H01L21/8238

    摘要： A semiconductor device includes a first and second channel patterns on a substrate, each of the first and second channel patterns including vertically-stacked semiconductor patterns; a first source/drain pattern connected to the first channel pattern; a second source/drain pattern connected to the second channel pattern, the first and second source/drain patterns having different conductivity types from each other; a first contact plug inserted in the first source/drain pattern, and a second contact plug inserted in the second source/drain pattern; a first interface layer interposed between the first source/drain pattern and the first contact plug; and a second interface layer interposed between the second source/drain pattern and the second contact plug, the first and second interface layers including different metallic elements from each other, a bottom portion of the second interface layer being positioned at a level that is lower than a bottom surface of a topmost one of the semiconductor patterns.

    SEMICONDUCTOR DEVICE
    6.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20220392899A1

    公开(公告)日：2022-12-08

    申请号：US17886878

    申请日：2022-08-12

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Yoon Tae HWANG ,  Sunjung LEE ,  Heonbok LEE ,  Geunwoo KIM ,  Wandon KIM

    IPC分类号： H01L27/092 ,  H01L21/8238

    摘要： A semiconductor device includes a first and second channel patterns on a substrate, each of the first and second channel patterns including vertically-stacked semiconductor patterns; a first source/drain pattern connected to the first channel pattern; a second source/drain pattern connected to the second channel pattern, the first and second source/drain patterns having different conductivity types; a first contact plug inserted in the first source/drain pattern, and a second contact plug inserted in the second source/drain pattern; a first interface layer interposed between the first source/drain pattern and the first contact plug; and a second interface layer interposed between the second source/drain pattern and the second contact plug, the first and second interface layers including different metallic elements from each other, a bottom portion of the second interface layer being positioned at a level that is lower than a bottom surface of a topmost one of the semiconductor patterns.

    DEVICE AND METHOD WITH TRANSFORMER MODEL IMPLEMENTATION
    7.
    发明申请
    DEVICE AND METHOD WITH TRANSFORMER MODEL IMPLEMENTATION 有权

    公开(公告)号：US20230138659A1

    公开(公告)日：2023-05-04

    申请号：US17887145

    申请日：2022-08-12

    申请人： SAMSUNG ELECTRONICS CO., LTD. ,  SNU R&DB FOUNDATION

    发明人： Jung Ho AHN ,  Sunjung LEE ,  Hailong LI ,  Jaewan CHOI

    IPC分类号： G06N3/04

    摘要： A device and method with transformer model implementation are provided. The electronic device includes a processor configured to perform an inference by implementing a transformer model including a plurality of encoders and a plurality of decoders, and a memory configured to store instructions to be executed by the processor. Each of the encoders and the decoders includes an attention block that determines an attention value. The processor is configured to perform a first sub-softmax tile-wise operation in the attention block, perform a reduction operation to determine an adjustment factor based on a resulting value of the first sub-softmax operation, and perform a second sub-softmax tile-wise operation based on a resulting value of the reduction operation.

    SEMICONDUCTOR DEVICE
    9.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20210104615A1

    公开(公告)日：2021-04-08

    申请号：US16893795

    申请日：2020-06-05

    申请人： Samsung Electronics Co., Ltd.

    发明人： Hyunsu KIM ,  Seonghun PARK ,  Sunjung LEE ,  Hun KIM ,  Namgil YOU

    IPC分类号： H01L29/49 ,  H01L23/532 ,  G11C5/02

    摘要： A semiconductor device includes a peripheral circuit region comprising a first substrate, circuit elements on the first substrate, a first insulating layer covering the circuit elements, and a contact plug passing through the first insulating layer and disposed to be connected to the first substrate; and a memory cell region comprising a second substrate, gate electrodes on the second substrate and stacked in a vertical direction, and channel structures passing through the gate electrodes, wherein the contact plug comprises a metal silicide layer disposed to contact the first substrate and having a first thickness, a first metal nitride layer on the metal silicide layer to contact the metal silicide layer and having a second thickness, greater than the first thickness, a second metal nitride layer on the first metal nitride layer, and a conductive layer on the second metal nitride layer.