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公开(公告)号：US10359793B2
公开(公告)日：2019-07-23
申请号：US15683896
申请日：2017-08-23
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Woo-Seok Kim , Tae-Ik Kim , Ji-Hyun Kim
Abstract: An oscillator control circuit includes a zero-temperature coefficient (ZTC) estimator estimating a ZTC voltage based on a supply voltage supplied to the oscillator and a frequency of an oscillation signal output by the oscillator. The ZTC voltage is the magnitude of the supply voltage VDD which corresponds to the ZTC condition for the oscillator. The ZTC estimator generates a bias control signal such that the magnitude of the supply voltage becomes the ZTC voltage.
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公开(公告)号：US09946290B2
公开(公告)日：2018-04-17
申请号：US15236931
申请日：2016-08-15
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sung-Jin Kim , Tae-Ik Kim , Ji-Hyun Kim
CPC classification number: G05F3/262
Abstract: A current reference circuit includes a reference current supply unit configured to generate a reference current having a target current level, a current-frequency converter configured to receive a first temporary reference current corresponding to the reference current from the reference current supply unit and to generate a first comparison clock signal in response to the first temporary reference current, and a first current compensation unit configured to generate a first current compensation signal used for the first temporary reference current to reach the target current level in response to a frequency of a reference clock signal and a frequency of the first comparison clock signal.
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公开(公告)号：US09847870B2
公开(公告)日：2017-12-19
申请号：US15197746
申请日：2016-06-29
Applicant: Samsung Electronics Co., Ltd.
Inventor： Do-Hyung Kim , Tae-Ik Kim
CPC classification number: H04L7/0331 , H03L7/18 , H04L27/20 , H04W4/80
Abstract: Provided are a semiconductor device including a modulator for PSK communication and a semiconductor device including a demodulator for PSK communication, and a PSK communication system. The semiconductor device includes a reference clock generator to generate a reference clock signal, a phase locked loop (PLL) to receive the reference clock signal and generate a first clock signal, an integer divider circuit to generate a second clock signal by delaying a rising edge of the reference clock signal by a product of a predetermined integer value included in transmission data and a phase interval, and a processing unit to generate a first transmission signal. The first transmission signal is phase-shifted from a first rising edge of the second clock signal. The phase interval is dependent on a ratio of the frequency of the first clock signal to the frequency of the reference clock signal.
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Patent Agency Ranking
公开(公告)号：US10352997B2
公开(公告)日：2019-07-16
申请号：US16053429
申请日：2018-08-02
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kang-Yeop Choo , Hyun-Ik Kim , Won-Seok Kim , Jung-Ho Kim , Ji-Hyun Kim , Tae-Ik Kim
IPC: G01R31/317
Abstract: A clock jitter measurement circuit includes: an internal signal generator configured to generate a single pulse signal and an internal clock signal which are both synchronized with an input clock signal received by the clock jitter measurement circuit, a plurality of edge delay cells serially connected to each other and configured to generate a plurality of edge detection signals respectively corresponding to a plurality of delay edges obtained by delaying an edge of the internal clock signal, a plurality of latch circuits configured to latch the single pulse signal in synchronization with the plurality of edge detection signals and output a plurality of sample signals, and a count sub-circuit configured to count a number of activated sample signals of the plurality of sample signals and output a count value based on the counted number of activated sample signals.
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公开(公告)号：US09473154B2
公开(公告)日：2016-10-18
申请号：US14632468
申请日：2015-02-26
Applicant: Samsung Electronics Co., Ltd.
Inventor： Woo-Seok Kim , Tae-Ik Kim , Ji-Hyun Kim
CPC classification number: H03L7/0891 , H02M3/04
Abstract: Provided are a semiconductor device and a phase-locked loop (PLL) including the same. The semiconductor device including an output node from which an output signal is output, a first transistor which has a drain connected to the output node and is gated by a first signal to increase a voltage level of the output node, a second transistor which has a drain connected to the output node, is gated by a second signal which is a complementary signal of the first signal, and reduces the voltage level of the output node, a pull-up circuit which provides a first compensation current varying according to the voltage level of the output node to a source of the first transistor, and a pull-down circuit which provides a second compensation current varying according to the voltage level of the output node to a source of the second transistor.
Abstract translation: 提供了包括其的半导体器件和锁相环（PLL）。 所述半导体器件包括输出信号被输出的输出节点，具有连接到所述输出节点的漏极并由第一信号选通以增加所述输出节点的电压电平的第一晶体管，具有 连接到输出节点的漏极由作为第一信号的互补信号的第二信号选通，并且降低输出节点的电压电平，提供根据电压电平变化的第一补偿电流的上拉电路 的输出节点连接到第一晶体管的源极;以及下拉电路，其提供根据输出节点的电压电平而变化到第二晶体管的源极的第二补偿电流。
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公开(公告)号：US20170060165A1
公开(公告)日：2017-03-02
申请号：US15236931
申请日：2016-08-15
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： SUNG-JIN KIM , Tae-Ik Kim , Ji-Hyun Kim
IPC: G05F3/26
CPC classification number: G05F3/262
Abstract: A current reference circuit includes a reference current supply unit configured to generate a reference current having a target current level, a current-frequency converter configured to receive a first temporary reference current corresponding to the reference current from the reference current supply unit and to generate a first comparison clock signal in response to the first temporary reference current, and a first current compensation unit configured to generate a first current compensation signal used for the first temporary reference current to reach the target current level in response to a frequency of a reference clock signal and a frequency of the first comparison clock signal.
Abstract translation: 电流参考电路包括被配置为产生具有目标电流电平的参考电流的参考电流供应单元，被配置为从参考电流供应单元接收对应于参考电流的第一临时参考电流的电流 - 频率转换器， 响应于第一临时参考电流的第一比较时钟信号，以及第一电流补偿单元，被配置为响应于参考时钟信号的频率产生用于第一临时参考电流的第一电流补偿信号以达到目标电流电平 以及第一比较时钟信号的频率。
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公开(公告)号：US09397644B2
公开(公告)日：2016-07-19
申请号：US14571944
申请日：2014-12-16
Applicant: Samsung Electronics Co., Ltd.
Inventor： Woo-Seok Kim , Tae-Ik Kim , Ji-Hyun Kim
CPC classification number: H03K5/00006 , H03K19/215
Abstract: A frequency doubler includes a voltage controlled oscillator outputting N (where, N is a natural number) signals having a first period and having different phases, and an XOR circuit receiving the N signals and outputting a signal having a second period that corresponds to a half of the first period, wherein the voltage controlled oscillator includes N nodes that correspond to the N signals and inverter units respectively connecting the N nodes, the N nodes are arranged so that, if a signal that starts from any one start node of the N nodes passes through the same number of the inverter units, it recurs to the corresponding start node, the XOR gate includes a first unit block set including N unit blocks that are connected to the same output node and match the N nodes in a one-to-one manner, and a second unit block set that is substantially the same as the first unit block set, wherein the first and second unit block sets share the output node.
Abstract translation: 倍频器包括输出具有第一周期且具有不同相位的N（其中，N是自然数）的电压控制振荡器，以及接收N信号的XOR电路，并输出具有对应于一半的第二周期的信号 其中压控振荡器包括对应于N个信号的N个节点和分别连接N个节点的逆变器单元，N个节点被布置成使得如果从N个节点的任何一个起始节点开始的信号 通过相同数量的逆变器单元，它重复到对应的起始节点，XOR门包括第一单元块集合，其包括连接到相同输出节点并且以一对一的方式匹配N个节点的N个单位块， 以及与第一单位块集基本相同的第二单位块集合，其中第一和第二单位块集共享输出节点。
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公开(公告)号：US20160049927A1
公开(公告)日：2016-02-18
申请号：US14571944
申请日：2014-12-16
Applicant: Samsung Electronics Co., Ltd.
Inventor： Woo-Seok Kim , Tae-Ik Kim , Ji-Hyun Kim
CPC classification number: H03K5/00006 , H03K19/215
Abstract: A frequency doubler includes a voltage controlled oscillator outputting N (where, N is a natural number) signals having a first period and having different phases, and an XOR circuit receiving the N signals and outputting a signal having a second period that corresponds to a half of the first period, wherein the voltage controlled oscillator includes N nodes that correspond to the N signals and inverter units respectively connecting the N nodes, the N nodes are arranged so that, if a signal that starts from any one start node of the N nodes passes through the same number of the inverter units, it recurs to the corresponding start node, the XOR gate includes a first unit block set including N unit blocks that are connected to the same output node and match the N nodes in a one-to-one manner, and a second unit block set that is substantially the same as the first unit block set, wherein the first and second unit block sets share the output node.
Abstract translation: 倍频器包括输出具有第一周期且具有不同相位的N（其中，N是自然数）的电压控制振荡器，以及接收N信号的XOR电路，并输出具有对应于一半的第二周期的信号 其中压控振荡器包括对应于N个信号的N个节点和分别连接N个节点的逆变器单元，N个节点被布置成使得如果从N个节点的任何一个起始节点开始的信号 通过相同数量的逆变器单元，它重复到对应的起始节点，XOR门包括第一单元块集合，其包括连接到相同输出节点并且以一对一的方式匹配N个节点的N个单位块， 以及与第一单位块集基本相同的第二单位块集合，其中第一和第二单位块集共享输出节点。
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