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    DISPLAY DRIVING CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING THE SAME
    1.
    发明申请
    DISPLAY DRIVING CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING THE SAME 审中-公开
    显示驱动电路和包括其的半导体器件

    公开(公告)号：US20160293076A1

    公开(公告)日：2016-10-06

    申请号：US14992257

    申请日：2016-01-11

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Woo-Seok Kim

    IPC: G09G3/00

    CPC classification number: G09G3/20 ,  G09G2330/08 ,  G09G2370/08

    Abstract: A display driving circuit includes a fault detector circuit which detects a fault in a circuit device and outputs a fault signal about the fault, a polarity selector circuit which stores polarity selection information and outputs a mode selection signal based on the polarity selection information, and a feedback circuit, wherein the feedback circuit includes an OR gate which receives an inverted signal of the mode selection signal and an inverted signal of the fault signal, an AND gate which receives the inverted signal of the mode selection signal and the fault signal, a first P-type transistor which is turned on or off by an output signal of the OR gate; and a first N-type transistor which is turned on or off by an output signal of the AND gate.

    Abstract translation: 显示驱动电路包括检测电路装置中的故障并输出故障的故障信号的故障检测电路，存储极性选择信息的极性选择电路，并根据极性选择信息输出模式选择信号， 反馈电路，其中反馈电路包括接收模式选择信号的反相信号和故障信号的反相信号的或门，接收模式选择信号和故障信号的反相信号的与门，第一 P型晶体管由OR门的输出信号导通或截止; 以及通过与门的输出信号导通或截止的第一N型晶体管。

    Circuit for driving gate of power MOS transistor
    4.
    发明授权
    Circuit for driving gate of power MOS transistor 有权
    用于驱动MOS晶体管栅极的电路

    公开(公告)号：US09236866B2

    公开(公告)日：2016-01-12

    申请号：US13934530

    申请日：2013-07-03

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyo-Sang Youn ,  Woo-Seok Kim

    IPC: H03B1/00 ,  H03K3/00 ,  H03K19/0175 ,  H02M3/158 ,  H02M3/155

    CPC classification number: H03K19/017509 ,  H02M3/155 ,  H02M3/158

    Abstract: A circuit for driving a gate of a power MOS transistor includes an adaptive pull-up unit and an adaptive pull-down unit. The adaptive pull-up unit is connected between a first power source voltage and the gate of the power MOS transistor. The adaptive pull-up unit maximizes pull-up current driving ability. The adaptive pull-down unit is connected between a second power source voltage and the gate of the power MOS transistor. The adaptive pull-down unit maximizes pull-down current driving ability.

    Abstract translation: 用于驱动功率MOS晶体管的栅极的电路包括自适应上拉单元和自适应下拉单元。 自适应上拉单元连接在第一电源电压和功率MOS晶体管的栅极之间。 自适应上拉单元最大化上拉电流驱动能力。 自适应下拉单元连接在第二电源电压和功率MOS晶体管的栅极之间。 自适应下拉单元使下拉电流驱动能力最大化。

    Temperature sensing circuits
    5.
    发明授权
    Temperature sensing circuits 有权

    公开(公告)号：US10001413B2

    公开(公告)日：2018-06-19

    申请号：US14569861

    申请日：2014-12-15

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Woo-Seok Kim

    IPC: G01K7/00 ,  G01K7/01

    CPC classification number: G01K7/01

    Abstract: Temperature sensing circuits are provided. The temperature sensing circuits may include a temperature sensing unit and a buffer unit. The temperature sensing unit may include a transistor that has a first pair of terminals having a first PN junction of the transistor therebetween and a second pair of terminals having a second PN junction of the transistor therebetween. The first pair of terminals are connected together. The temperature sensing unit may output a first temperature sensing voltage comprising a voltage between the second pair of terminals at a first node. The buffer unit may be connected to the first node. The buffer unit may have a cascode follower structure and may output a second temperature sensing voltage that has a magnitude proportional to a magnitude of the first temperature sensing voltage at a second node.

    CIRCUIT FOR DRIVING GATE OF POWER MOS TRANSISTOR
    6.
    发明申请
    CIRCUIT FOR DRIVING GATE OF POWER MOS TRANSISTOR 有权
    功率MOS晶体管驱动电路电路

    公开(公告)号：US20140015501A1

    公开(公告)日：2014-01-16

    申请号：US13934530

    申请日：2013-07-03

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： HYO-SANG YOUN ,  Woo-Seok Kim

    IPC: H03K19/0175 ,  H02M3/158

    CPC classification number: H03K19/017509 ,  H02M3/155 ,  H02M3/158

    Abstract: A circuit for driving a gate of a power MOS transistor includes an adaptive pull-up unit and an adaptive pull-down unit. The adaptive pull-up unit is connected between a first power source voltage and the gate of the power MOS transistor. The adaptive pull-up unit maximizes pull-up current driving ability. The adaptive pull-down unit is connected between a second power source voltage and the gate of the power MOS transistor. The adaptive pull-down unit maximizes pull-down current driving ability.

    Abstract translation: 用于驱动功率MOS晶体管的栅极的电路包括自适应上拉单元和自适应下拉单元。 自适应上拉单元连接在第一电源电压和功率MOS晶体管的栅极之间。 自适应上拉单元最大化上拉电流驱动能力。 自适应下拉单元连接在第二电源电压和功率MOS晶体管的栅极之间。 自适应下拉单元使下拉电流驱动能力最大化。

    Frequency doubler
    7.
    发明授权
    Frequency doubler 有权
    倍频器

    公开(公告)号：US09397644B2

    公开(公告)日：2016-07-19

    申请号：US14571944

    申请日：2014-12-16

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Woo-Seok Kim ,  Tae-Ik Kim ,  Ji-Hyun Kim

    IPC: H03B19/00 ,  H03K5/00 ,  H03K19/21

    CPC classification number: H03K5/00006 ,  H03K19/215

    Abstract: A frequency doubler includes a voltage controlled oscillator outputting N (where, N is a natural number) signals having a first period and having different phases, and an XOR circuit receiving the N signals and outputting a signal having a second period that corresponds to a half of the first period, wherein the voltage controlled oscillator includes N nodes that correspond to the N signals and inverter units respectively connecting the N nodes, the N nodes are arranged so that, if a signal that starts from any one start node of the N nodes passes through the same number of the inverter units, it recurs to the corresponding start node, the XOR gate includes a first unit block set including N unit blocks that are connected to the same output node and match the N nodes in a one-to-one manner, and a second unit block set that is substantially the same as the first unit block set, wherein the first and second unit block sets share the output node.

    Abstract translation: 倍频器包括输出具有第一周期且具有不同相位的N（其中，N是自然数）的电压控制振荡器，以及接收N信号的XOR电路，并输出具有对应于一半的第二周期的信号 其中压控振荡器包括对应于N个信号的N个节点和分别连接N个节点的逆变器单元，N个节点被布置成使得如果从N个节点的任何一个起始节点开始的信号 通过相同数量的逆变器单元，它重复到对应的起始节点，XOR门包括第一单元块集合，其包括连接到相同输出节点并且以一对一的方式匹配N个节点的N个单位块， 以及与第一单位块集基本相同的第二单位块集合，其中第一和第二单位块集共享输出节点。

    FREQUENCY DOUBLER
    8.
    发明申请
    FREQUENCY DOUBLER 有权
    频率双打

    公开(公告)号：US20160049927A1

    公开(公告)日：2016-02-18

    申请号：US14571944

    申请日：2014-12-16

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Woo-Seok Kim ,  Tae-Ik Kim ,  Ji-Hyun Kim

    IPC: H03K5/00 ,  H03K19/21

    CPC classification number: H03K5/00006 ,  H03K19/215

    Abstract: A frequency doubler includes a voltage controlled oscillator outputting N (where, N is a natural number) signals having a first period and having different phases, and an XOR circuit receiving the N signals and outputting a signal having a second period that corresponds to a half of the first period, wherein the voltage controlled oscillator includes N nodes that correspond to the N signals and inverter units respectively connecting the N nodes, the N nodes are arranged so that, if a signal that starts from any one start node of the N nodes passes through the same number of the inverter units, it recurs to the corresponding start node, the XOR gate includes a first unit block set including N unit blocks that are connected to the same output node and match the N nodes in a one-to-one manner, and a second unit block set that is substantially the same as the first unit block set, wherein the first and second unit block sets share the output node.

    Abstract translation: 倍频器包括输出具有第一周期且具有不同相位的N（其中，N是自然数）的电压控制振荡器，以及接收N信号的XOR电路，并输出具有对应于一半的第二周期的信号 其中压控振荡器包括对应于N个信号的N个节点和分别连接N个节点的逆变器单元，N个节点被布置成使得如果从N个节点的任何一个起始节点开始的信号 通过相同数量的逆变器单元，它重复到对应的起始节点，XOR门包括第一单元块集合，其包括连接到相同输出节点并且以一对一的方式匹配N个节点的N个单位块， 以及与第一单位块集基本相同的第二单位块集合，其中第一和第二单位块集共享输出节点。

    Semiconductor device and phase locked loop including the same
    9.
    发明授权
    Semiconductor device and phase locked loop including the same 有权
    半导体器件和包括相同的锁相环

    公开(公告)号：US09473154B2

    公开(公告)日：2016-10-18

    申请号：US14632468

    申请日：2015-02-26

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Woo-Seok Kim ,  Tae-Ik Kim ,  Ji-Hyun Kim

    IPC: H03L7/06 ,  H03L7/089 ,  H02M3/04

    CPC classification number: H03L7/0891 ,  H02M3/04

    Abstract: Provided are a semiconductor device and a phase-locked loop (PLL) including the same. The semiconductor device including an output node from which an output signal is output, a first transistor which has a drain connected to the output node and is gated by a first signal to increase a voltage level of the output node, a second transistor which has a drain connected to the output node, is gated by a second signal which is a complementary signal of the first signal, and reduces the voltage level of the output node, a pull-up circuit which provides a first compensation current varying according to the voltage level of the output node to a source of the first transistor, and a pull-down circuit which provides a second compensation current varying according to the voltage level of the output node to a source of the second transistor.

    Abstract translation: 提供了包括其的半导体器件和锁相​​环（PLL）。 所述半导体器件包括输出信号被输出的输出节点，具有连接到所述输出节点的漏极并由第一信号选通以增加所述输出节点的电压电平的第一晶体管，具有 连接到输出节点的漏极由作为第一信号的互补信号的第二信号选通，并且降低输出节点的电压电平，提供根据电压电平变化的第一补偿电流的上拉电路 的输出节点连接到第一晶体管的源极;以及下拉电路，其提供根据输出节点的电压电平而变化到第二晶体管的源极的第二补偿电流。

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