公开(公告)号：US08962455B2

公开(公告)日：2015-02-24

申请号：US13920181

申请日：2013-06-18

申请人： SAMSUNG Electronics Co., Ltd.

发明人： Sang-Hyun Choi ,  Jin-Ho Noh ,  Yoon-Ho Son ,  Dae-Hyuk Chung ,  In-Seak Hwang ,  Tae-Joon Park ,  Tae-Ho Hwang

IPC分类号： H01L21/36 ,  H01L21/768 ,  H01L21/28 ,  H01L29/78 ,  H01L29/423 ,  H01L27/108

CPC分类号： H01L21/76841 ,  H01L21/28158 ,  H01L27/10876 ,  H01L27/10891 ,  H01L29/4236 ,  H01L29/7827

摘要： A method of fabricating a semiconductor device includes forming a first preliminary gate barrier layer and a first preliminary gate electrode recessed to have a first depth from the surface of the substrate within a gate trench, removing an upper portion of the first preliminary gate electrode by means of a first wet etching process using a first etchant to form a second preliminary gate electrode recessed to have a second depth greater than the first depth, and removing an upper portion of the first preliminary gate barrier layer and an upper portion of the second preliminary gate electrode by means of a second wet etching process using a second etchant to form a gate electrode and a gate barrier layer recessed to a third depth greater than the second depth.

摘要翻译： 制造半导体器件的方法包括：形成第一预栅极势垒层和第一预栅极电极，所述第一预栅极电极凹陷以在栅极沟槽内具有来自衬底的表面的第一深度，通过装置去除第一预栅极的上部 使用第一蚀刻剂形成凹陷以具有大于第一深度的第二深度的第二预选栅电极的第一湿蚀刻工艺，以及去除第一预栅极势垒层的上部和第二预选栅极的上部 电极通过使用第二蚀刻剂的第二湿蚀刻工艺形成栅电极和凹陷到大于第二深度的第三深度的栅极势垒层。

公开(公告)号：US09390961B2

公开(公告)日：2016-07-12

申请号：US14481932

申请日：2014-09-10

申请人： Samsung Electronics Co., Ltd.

发明人： Mong-Sup Lee ,  Byoung-Yong Gwak ,  Byung-Ho Kwak ,  Yoon-Kyung Kim ,  Tae-Joon Park ,  Byung-Sul Ryu ,  In-Seak Hwang

IPC分类号： H01L21/70 ,  H01L21/762 ,  H01L27/108

CPC分类号： H01L21/762 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10888

摘要： Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes a first bit line structure extending in a first direction, a second bit line structure extending in the first direction and spaced apart from the first bit line structure, a storage contact plug located between the first bit line structure and the second bit line structure, and extending in a second direction perpendicular to the first direction, a first plug insulator located between the first bit line structure and the second bit line structure, and configured to contact a side surface extending in the second direction of the storage contact plug, and a plug isolation pattern located between the first bit line structure and the first plug insulator.

摘要翻译： 提供半导体器件及其制造方法。 半导体器件包括沿第一方向延伸的第一位线结构，在第一方向上延伸并与第一位线结构间隔开的第二位线结构，位于第一位线结构和第二位之间的存储接触插塞 线结构，并且在垂直于第一方向的第二方向上延伸;第一插塞绝缘体，位于第一位线结构和第二位线结构之间，并且被配置为接触沿着存储接触插塞的第二方向延伸的侧表面 以及位于第一位线结构和第一插塞绝缘体之间的插头隔离图案。