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    Semiconductor memory devices and methods of forming the same
    1.
    发明授权
    Semiconductor memory devices and methods of forming the same 有权
    半导体存储器件及其形成方法

    公开(公告)号：US09287349B2

    公开(公告)日：2016-03-15

    申请号：US13688840

    申请日：2012-11-29

    申请人： Samsung Electronics Co., Ltd.

    发明人： Hyong-Soo Kim ,  Byoung-Yong Gwak ,  Kukhan Yoon

    IPC分类号： H01L49/02 ,  H01L27/108 ,  H01L43/12 ,  H01L29/02

    CPC分类号： H01L28/60 ,  H01L27/10805 ,  H01L27/10852 ,  H01L28/91

    摘要： According to example embodiments of inventive concepts, method of forming a semiconductor memory devices includes sequentially forming a first mold layer, a first support layer, a second mold layer, and a second support layer on a substrate, forming lower electrodes penetrating the second support layer, the second mold layer, the first support layer, and the first mold layer on the substrate, patterning the second support layer to form a second support pattern including an opening, removing the second mold layer to expose portions of sidewalls of the lower electrodes, and etching the exposed sidewalls of the lower electrodes.

    摘要翻译： 根据本发明构思的示例性实施例，形成半导体存储器件的方法包括在衬底上顺序地形成第一模具层，第一支撑层，第二模具层和第二支撑层，形成穿透第二支撑层的下部电极 第二模具层，第一支撑层和第一模具层，图案化第二支撑层以形成包括开口的第二支撑图案，去除第二模具层以暴露下部电极的侧壁部分， 并蚀刻下电极的暴露的侧壁。

    Method of forming fine patterns of semiconductor device
    2.
    发明授权
    Method of forming fine patterns of semiconductor device 有权
    形成半导体器件精细图案的方法

    公开(公告)号：US09070640B2

    公开(公告)日：2015-06-30

    申请号：US14079658

    申请日：2013-11-14

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Byoung-Yong Gwak

    IPC分类号： H01L21/4763 ,  H01L21/311 ,  H01L21/033 ,  H01L27/108 ,  H01L27/115

    CPC分类号： H01L21/31144 ,  H01L21/0337 ,  H01L27/10852 ,  H01L27/1158

    摘要： A method of forming fine patterns includes patterning a hard mask layer and a buffer mask layer sequentially stacked on a lower mask layer to form first openings, forming sacrificial patterns filling the first openings and protruding from a top surface of the buffer mask layer, forming a spacer pattern filling a space between two adjacent sacrificial patterns and having gaps each of which exposes a portion of the buffer mask layer between at least three adjacent sacrificial patterns, etching portions of the buffer mask layer exposed by the gaps of the spacer pattern to form enlarged holes, etching portions of the hard mask layer exposed by the enlarged holes to form second openings, and subsequently etching the lower layer using the hard mask layer as an etch mask.

    摘要翻译： 形成精细图案的方法包括将顺序层叠在下掩模层上的硬掩模层和缓冲掩模层图案化以形成第一开口，形成填充第一开口并从缓冲掩模层的顶表面突出的牺牲图案，形成 间隔图案填充两个相邻的牺牲图案之间的间隔，并且具有间隙，每个凹槽将缓冲掩模层的一部分暴露在至少三个相邻的牺牲图案之间，由间隔图案的间隙暴露的缓冲掩模层的蚀刻部分以形成扩大 蚀刻由扩大的孔暴露的硬掩模层的部分以形成第二开口，随后使用硬掩模层作为蚀刻掩模蚀刻下层。

    Semiconductor devices having plug insulators
    3.
    发明授权
    Semiconductor devices having plug insulators 有权
    具有插头绝缘体的半导体器件

    公开(公告)号：US09390961B2

    公开(公告)日：2016-07-12

    申请号：US14481932

    申请日：2014-09-10

    申请人： Samsung Electronics Co., Ltd.

    发明人： Mong-Sup Lee ,  Byoung-Yong Gwak ,  Byung-Ho Kwak ,  Yoon-Kyung Kim ,  Tae-Joon Park ,  Byung-Sul Ryu ,  In-Seak Hwang

    IPC分类号： H01L21/70 ,  H01L21/762 ,  H01L27/108

    CPC分类号： H01L21/762 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10888

    摘要： Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes a first bit line structure extending in a first direction, a second bit line structure extending in the first direction and spaced apart from the first bit line structure, a storage contact plug located between the first bit line structure and the second bit line structure, and extending in a second direction perpendicular to the first direction, a first plug insulator located between the first bit line structure and the second bit line structure, and configured to contact a side surface extending in the second direction of the storage contact plug, and a plug isolation pattern located between the first bit line structure and the first plug insulator.

    摘要翻译： 提供半导体器件及其制造方法。 半导体器件包括沿第一方向延伸的第一位线结构，在第一方向上延伸并与第一位线结构间隔开的第二位线结构，位于第一位线结构和第二位之间的存储接触插塞 线结构，并且在垂直于第一方向的第二方向上延伸;第一插塞绝缘体，位于第一位线结构和第二位线结构之间，并且被配置为接触沿着存储接触插塞的第二方向延伸的侧表面 以及位于第一位线结构和第一插塞绝缘体之间的插头隔离图案。