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公开(公告)号：US11222709B2
公开(公告)日：2022-01-11
申请号：US16916463
申请日：2020-06-30
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Taekwoon Kim , Wonhyung Song , Jangseok Choi
Abstract: A memory system includes a memory module and a memory controller. The memory module includes data chips that store data and are assigned to a first sub-channel that generates a first code word or a second sub-channel that generates a second code word, where the first code word and the second code are used to fill a single cache line. The memory controller, upon detection of a hard-fail data chip among the data chips, copies data from the hard-fail data chip to the ECC chip, releases mapping between the hard-fail data chip and corresponding I/O, and defines new mapping between the ECC chip and the corresponding I/O pins.
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公开(公告)号：US11068347B2
公开(公告)日：2021-07-20
申请号：US16878793
申请日：2020-05-20
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hyunjoong Kim , Taekwoon Kim , Younghoe Kim , Wonhyung Song , Jangseok Choi , Joonseok Choi
Abstract: A memory controller configured to control a memory module including a plurality of memory devices which constitute a first channel and a second channel includes an error correction code (ECC) engine, and a control circuit configured to control the ECC engine. The ECC engine is configured to generate a codeword including a plurality of symbols by adaptively constructing, based on device information including mapping information, each of the plurality of symbols from a predetermined number of data bits received via a plurality of input/output pads of each of the plurality of memory devices, and transmit the codeword to the memory module. The mapping information indicates whether each of the plurality of input/output pads is mapped to the same symbol among the plurality of symbols or different symbols among the plurality of symbols. Each of the plurality of symbols corresponds to a unit of error correction of the ECC engine.
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3.发明公开公开(公告)号：US20240345944A1
公开(公告)日：2024-10-17
申请号：US18634559
申请日：2024-04-12
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： KI-HEUNG KIM , Taeyoung Oh , Taekwoon Kim , Jinseong Yun , Yoonjae Jeong , Hyongryol Hwang
IPC: G06F12/02
CPC classification number: G06F12/0223 , G06F2212/202
Abstract: A method of operating a memory configured to communicate with a memory controller, the method includes: temporarily storing a unique identification (ID) for each of a plurality of memory devices included in the memory to each of the plurality of memory devices; selecting a target memory device from among the plurality of memory devices; and permanently or substantially permanently programming, in the target memory device, a unique ID corresponding to the target memory device.
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公开(公告)号：US20210133028A1
公开(公告)日：2021-05-06
申请号：US16878793
申请日：2020-05-20
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hyunjoong Kim , Taekwoon Kim , Younghoe Kim , Wonhyung Song , Jangseok Choi , Joonseok Choi
IPC: G06F11/10
Abstract: A memory controller configured to control a memory module including a plurality of memory devices which constitute a first channel and a second channel includes an error correction code (ECC) engine, and a control circuit configured to control the ECC engine. The ECC engine is configured to generate a codeword including a plurality of symbols by adaptively constructing, based on device information including mapping information, each of the plurality of symbols from a predetermined number of data bits received via a plurality of input/output pads of each of the plurality of memory devices, and transmit the codeword to the memory module. The mapping information indicates whether each of the plurality of input/output pads is mapped to the same symbol among the plurality of symbols or different symbols among the plurality of symbols. Each of the plurality of symbols corresponds to a unit of error correction of the ECC engine.
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公开(公告)号：US11756646B2
公开(公告)日：2023-09-12
申请号：US17541645
申请日：2021-12-03
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Taekwoon Kim , Wonhyung Song , Jangseok Choi
CPC classification number: G11C29/42 , G11C29/12015 , G11C29/32 , G11C29/44 , G11C2029/1206 , G11C2029/4402
Abstract: A memory system includes a memory module and a memory controller. The memory module includes data chips that store data and are assigned to a first sub-channel that generates a first code word or a second sub-channel that generates a second code word, where the first code word and the second code are used to fill a single cache line. The memory controller, upon detection of a hard-fail data chip among the data chips, copies data from the hard-fail data chip to the ECC chip, releases mapping between the hard-fail data chip and corresponding I/O, and defines new mapping between the ECC chip and the corresponding I/O pins.
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Patent Agency Ranking
公开(公告)号：US20210089395A1
公开(公告)日：2021-03-25
申请号：US16861312
申请日：2020-04-29
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Wonhyung Song , Taekwoon Kim , Hosung Yoon , Yoojung Lee , Jangseok Choi
Abstract: A memory module includes first memory chips, each having a first input/output width, and configured to store data, a second memory chip having a second input/output width and configured to store an error correction code for correcting an error in the data, and a driver circuit configured to receive a clock signal, a command, and an address from a memory controller and to transmit the clock signal, the command, and the address to the first memory chips and the second memory chip. An address depth of each of the first memory chips and an address depth of the second memory chip are different from each other.
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7.发明授权公开(公告)号：US12216909B2
公开(公告)日：2025-02-04
申请号：US17992516
申请日：2022-11-22
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Taekwoon Kim , Youngsoo Sohn
IPC: G06F3/06
Abstract: A memory module including a row hammer counter chip, a memory system including the same, and a method of operating the memory system are provided. The memory module includes a plurality of data chips each of which is configured to store a data set corresponding to a plurality of burst lengths, and at least one row hammer counter chip including counter memory cells each of which is connected to a word line, among a plurality of word lines, for each of the plurality of data chips, wherein the at least one row hammer counter chip is configured to store in each of the counter memory cells connected to the word line, a number of times the word line is accessed for each of the plurality of data chips during a row hammer monitoring time frame.
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8.发明公开公开(公告)号：US20240289058A1
公开(公告)日：2024-08-29
申请号：US18590324
申请日：2024-02-28
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Ki-Heung KIM , Taeyoung Oh , Taekwoon Kim , Jinseong Yun , Yoonjae Jeong , Hyongryol Hwang
IPC: G06F3/06
CPC classification number: G06F3/0659 , G06F3/0604 , G06F3/0683
Abstract: A method of operating a memory module that communicates with a memory controller includes: entering a one-time programmable (OTP) addressing mode based on an OTP command received from the memory controller; determining whether a guard key sequence is satisfied based on a plurality of mode register commands received from the memory controller; and programming, based on a determination that the guard key sequence is satisfied, a unique identifier (ID), corresponding to a target memory device, into the target memory device, among a plurality of memory devices included in the memory module.
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公开(公告)号：US20230386597A1
公开(公告)日：2023-11-30
申请号：US18365868
申请日：2023-08-04
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Taekwoon Kim , Wonhyung Song , Jangseok Choi
CPC classification number: G11C29/42 , G11C29/44 , G11C29/32 , G11C29/12015 , G11C2029/4402 , G11C2029/1206
Abstract: A memory system includes a memory module and a memory controller. The memory module includes data chips that store data and are assigned to a first sub-channel that generates a first code word or a second sub-channel that generates a second code word, where the first code word and the second code are used to fill a single cache line. The memory controller, upon detection of a hard-fail data chip among the data chips, copies data from the hard-fail data chip to the ECC chip, releases mapping between the hard-fail data chip and corresponding I/O, and defines new mapping between the ECC chip and the corresponding I/O pins.
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公开(公告)号：US11507456B2
公开(公告)日：2022-11-22
申请号：US17487506
申请日：2021-09-28
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Wonhyung Song , Taekwoon Kim , Hosung Yoon , Yoojung Lee , Jangseok Choi
Abstract: A memory module includes first memory chips, each having a first input/output width, and configured to store data, a second memory chip having a second input/output width and configured to store an error correction code for correcting an error in the data, and a driver circuit configured to receive a clock signal, a command, and an address from a memory controller and to transmit the clock signal, the command, and the address to the first memory chips and the second memory chip. An address depth of each of the first memory chips and an address depth of the second memory chip are different from each other.
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